mirror of https://github.com/acidanthera/audk.git
181 lines
5.7 KiB
C
181 lines
5.7 KiB
C
/** @file
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SPI flash device header file.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SPI_FLASH_DEVICE_H_
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#define _SPI_FLASH_DEVICE_H_
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#include <PiDxe.h>
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#include <Protocol/Spi.h>
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#include <Protocol/FirmwareVolumeBlock.h>
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//
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// Supported SPI Flash Devices
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//
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typedef enum {
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EnumSpiFlash25L3205D, // Macronix 32Mbit part
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EnumSpiFlashW25Q32, // Winbond 32Mbit part
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EnumSpiFlashW25X32, // Winbond 32Mbit part
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EnumSpiFlashAT25DF321, // Atmel 32Mbit part
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EnumSpiFlashQH25F320, // Intel 32Mbit part
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EnumSpiFlash25VF064C, // SST 64Mbit part
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EnumSpiFlashM25PX64, // NUMONYX 64Mbit part
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EnumSpiFlashAT25DF641, // Atmel 64Mbit part
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EnumSpiFlashS25FL064K, // Spansion 64Mbit part
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EnumSpiFlash25L6405D, // Macronix 64Mbit part
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EnumSpiFlashW25Q64, // Winbond 64Mbit part
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EnumSpiFlashW25X64, // Winbond 64Mbit part
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EnumSpiFlashQH25F640, // Intel 64Mbit part
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EnumSpiFlashMax
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} SPI_FLASH_TYPES_SUPPORTED;
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//
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// Flash Device commands
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//
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// If a supported device uses a command different from the list below, a device specific command
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// will be defined just below it's JEDEC id section.
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//
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#define SPI_COMMAND_WRITE 0x02
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#define SPI_COMMAND_WRITE_AAI 0xAD
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#define SPI_COMMAND_READ 0x03
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#define SPI_COMMAND_ERASE 0x20
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#define SPI_COMMAND_WRITE_DISABLE 0x04
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#define SPI_COMMAND_READ_S 0x05
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#define SPI_COMMAND_WRITE_ENABLE 0x06
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#define SPI_COMMAND_READ_ID 0xAB
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#define SPI_COMMAND_JEDEC_ID 0x9F
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#define SPI_COMMAND_WRITE_S_EN 0x50
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#define SPI_COMMAND_WRITE_S 0x01
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#define SPI_COMMAND_CHIP_ERASE 0xC7
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#define SPI_COMMAND_BLOCK_ERASE 0xD8
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//
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// Flash JEDEC device ids
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//
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// SST 8Mbit part
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//
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#define SPI_SST25VF080B_ID1 0xBF
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#define SPI_SST25VF080B_ID2 0x25
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#define SPI_SST25VF080B_ID3 0x8E
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//
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// SST 16Mbit part
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//
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#define SPI_SST25VF016B_ID1 0xBF
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#define SPI_SST25VF016B_ID2 0x25
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#define SPI_SST25V016BF_ID3 0x41
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//
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// Macronix 32Mbit part
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//
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// MX25 part does not support WRITE_AAI comand (0xAD)
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//
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#define SPI_MX25L3205_ID1 0xC2
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#define SPI_MX25L3205_ID2 0x20
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#define SPI_MX25L3205_ID3 0x16
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//
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// Intel 32Mbit part bottom boot
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//
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#define SPI_QH25F320_ID1 0x89
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#define SPI_QH25F320_ID2 0x89
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#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot
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//
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// Intel 64Mbit part bottom boot
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//
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#define SPI_QH25F640_ID1 0x89
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#define SPI_QH25F640_ID2 0x89
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#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot
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//
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// QH part does not support command 0x20 for erase; only 0xD8 (sector erase)
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// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)
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// 0x40 command ignored if address outside of parameter block range
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//
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#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40
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//
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// Winbond 32Mbit part
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//
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#define SPI_W25X32_ID1 0xEF
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#define SPI_W25X32_ID2 0x30 // Memory Type
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#define SPI_W25X32_ID3 0x16 // Capacity
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#define SF_DEVICE_ID1_W25Q32 0x16
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//
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// Winbond 64Mbit part
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//
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#define SPI_W25X64_ID1 0xEF
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#define SPI_W25X64_ID2 0x30 // Memory Type
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#define SPI_W25X64_ID3 0x17 // Capacity
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#define SF_DEVICE_ID0_W25QXX 0x40
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#define SF_DEVICE_ID1_W25Q64 0x17
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//
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// Winbond 128Mbit part
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//
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#define SF_DEVICE_ID0_W25Q128 0x40
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#define SF_DEVICE_ID1_W25Q128 0x18
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//
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// Atmel 32Mbit part
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//
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#define SPI_AT26DF321_ID1 0x1F
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#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density
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#define SPI_AT26DF321_ID3 0x00
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#define SF_VENDOR_ID_ATMEL 0x1F
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#define SF_DEVICE_ID0_AT25DF641 0x48
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#define SF_DEVICE_ID1_AT25DF641 0x00
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//
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// SST 8Mbit part
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//
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#define SPI_SST25VF080B_ID1 0xBF
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#define SPI_SST25VF080B_ID2 0x25
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#define SPI_SST25VF080B_ID3 0x8E
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#define SF_DEVICE_ID0_25VF064C 0x25
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#define SF_DEVICE_ID1_25VF064C 0x4B
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//
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// SST 16Mbit part
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//
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#define SPI_SST25VF016B_ID1 0xBF
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#define SPI_SST25VF016B_ID2 0x25
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#define SPI_SST25V016BF_ID3 0x41
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//
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// Winbond 32Mbit part
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//
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#define SPI_W25X32_ID1 0xEF
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#define SPI_W25X32_ID2 0x30 // Memory Type
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#define SPI_W25X32_ID3 0x16 // Capacity
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#define SF_VENDOR_ID_MX 0xC2
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#define SF_DEVICE_ID0_25L6405D 0x20
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#define SF_DEVICE_ID1_25L6405D 0x17
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#define SF_VENDOR_ID_NUMONYX 0x20
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#define SF_DEVICE_ID0_M25PX64 0x71
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#define SF_DEVICE_ID1_M25PX64 0x17
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//
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// Spansion 64Mbit part
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//
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#define SF_VENDOR_ID_SPANSION 0xEF
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#define SF_DEVICE_ID0_S25FL064K 0x40
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#define SF_DEVICE_ID1_S25FL064K 0x00
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//
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// index for prefix opcodes
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//
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#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE
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#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN
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#define BIOS_CTRL 0xDC
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#define PFAB_CARD_DEVICE_ID 0x5150
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#define PFAB_CARD_VENDOR_ID 0x8086
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#define PFAB_CARD_SETUP_REGISTER 0x40
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#define PFAB_CARD_SETUP_BYTE 0x0d
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#endif
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