mirror of https://github.com/acidanthera/audk.git
128 lines
6.6 KiB
C
128 lines
6.6 KiB
C
/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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SioInit.c
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Abstract:
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Functions for LpcSio initialization
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--*/
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#include "PlatformSerialPortLib.h"
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#include "SioInit.h"
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typedef struct {
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UINT8 Register;
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UINT8 Value;
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} EFI_SIO_TABLE;
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EFI_SIO_TABLE mSioTableWpcn381u[] = {
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{0x29, 0x0A0},
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
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{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
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{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
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{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
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{0x21, 0x001}, // Global Device Enable
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{0x26, 0x000}
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};
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EFI_SIO_TABLE mSioTableWdcp376[] = {
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{0x29, 0x0A0},
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
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{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
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{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
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{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
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{0x21, 0x001}, // Global Device Enable
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{0x26, 0x000},
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard
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{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB
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{WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB
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{WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1
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{0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
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{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse
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{WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12
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{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit
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};
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/**
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Initialization for SIO.
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@param FfsHeader FV this PEIM was loaded from.
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@param PeiServices General purpose services available to every PEIM.
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None
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**/
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VOID
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InitializeSio (
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VOID
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)
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{
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UINT16 Index;
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UINT16 IndexPort;
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UINT16 DataPort;
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//
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// Super I/O initialization for Winbond WPCN381U
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//
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IndexPort = WPCN381U_CONFIG_INDEX;
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DataPort = WPCN381U_CONFIG_DATA;
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//
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// Check for Winbond WPCN381U
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//
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IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20
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if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4
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//
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// Configure WPCN381U SIO
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//
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for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
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IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
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IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
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}
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}
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if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1
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//
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// Configure WDCP376 SIO
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//
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for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {
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IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);
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IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);
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}
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}
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return;
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}
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