mirror of https://github.com/acidanthera/audk.git
88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
/** @file
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Enhanced Intel SpeedStep feature.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuCommonFeatures.h"
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/**
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Detects if Enhanced Intel SpeedStep feature supported on current processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@retval TRUE Enhanced Intel SpeedStep feature is supported.
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@retval FALSE Enhanced Intel SpeedStep feature is not supported.
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@note This service could be called by BSP/APs.
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**/
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BOOLEAN
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EFIAPI
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EistSupport (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData OPTIONAL
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)
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{
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return (CpuInfo->CpuIdVersionInfoEcx.Bits.EIST == 1);
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}
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/**
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Initializes Enhanced Intel SpeedStep feature to specific state.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@param[in] State If TRUE, then the Enhanced Intel SpeedStep feature
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must be enabled.
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If FALSE, then the Enhanced Intel SpeedStep feature
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must be disabled.
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@retval RETURN_SUCCESS Enhanced Intel SpeedStep feature is initialized.
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@note This service could be called by BSP only.
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**/
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RETURN_STATUS
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EFIAPI
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EistInitialize (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData, OPTIONAL
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IN BOOLEAN State
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)
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{
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//
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// The scope of the MSR_IA32_MISC_ENABLE is core for below processor type, only program
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// MSR_IA32_MISC_ENABLE for thread 0 in each core.
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//
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if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
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IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
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IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
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if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
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return RETURN_SUCCESS;
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}
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}
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CPU_REGISTER_TABLE_WRITE_FIELD (
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ProcessorNumber,
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Msr,
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MSR_IA32_MISC_ENABLE,
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MSR_IA32_MISC_ENABLE_REGISTER,
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Bits.EIST,
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(State) ? 1 : 0
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);
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return RETURN_SUCCESS;
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}
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