mirror of https://github.com/acidanthera/audk.git
120 lines
4.5 KiB
C
120 lines
4.5 KiB
C
/** @file
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Protected Processor Inventory Number(PPIN) feature.
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Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuCommonFeatures.h"
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/**
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Detects if Protected Processor Inventory Number feature supported on current
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processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@retval TRUE Protected Processor Inventory Number feature is supported.
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@retval FALSE Protected Processor Inventory Number feature is not supported.
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@note This service could be called by BSP/APs.
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**/
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BOOLEAN
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EFIAPI
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PpinSupport (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData OPTIONAL
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)
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{
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MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
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if ((CpuInfo->DisplayFamily == 0x06) &&
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((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
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(CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product
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(CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4
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(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
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(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
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(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
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)) {
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//
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// Check whether platform support this feature.
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//
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PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
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return (PlatformInfo.Bits.PPIN_CAP != 0);
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}
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return FALSE;
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}
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/**
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Initializes Protected Processor Inventory Number feature to specific state.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@param[in] State If TRUE, then the Protected Processor Inventory
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Number feature must be enabled.
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If FALSE, then the Protected Processor Inventory
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Number feature must be disabled.
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@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
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initialized.
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@retval RETURN_DEVICE_ERROR Device can't change state because it has been
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locked.
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**/
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RETURN_STATUS
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EFIAPI
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PpinInitialize (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData, OPTIONAL
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IN BOOLEAN State
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)
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{
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MSR_IVY_BRIDGE_PPIN_CTL_REGISTER MsrPpinCtrl;
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//
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// Check whether device already lock this register.
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// If already locked, just base on the request state and
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// the current state to return the status.
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//
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MsrPpinCtrl.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
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if (MsrPpinCtrl.Bits.LockOut != 0) {
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return MsrPpinCtrl.Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;
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}
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//
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// Support function already check the processor which support PPIN feature, so this function not need
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// to check the processor again.
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//
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// The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for
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// thread 0 core 0 in each package.
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//
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if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {
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return RETURN_SUCCESS;
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}
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CPU_REGISTER_TABLE_WRITE_FIELD (
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ProcessorNumber,
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Msr,
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MSR_IVY_BRIDGE_PPIN_CTL,
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MSR_IVY_BRIDGE_PPIN_CTL_REGISTER,
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Bits.Enable_PPIN,
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(State) ? 1 : 0
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);
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return RETURN_SUCCESS;
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}
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