mirror of https://github.com/acidanthera/audk.git
155 lines
6.4 KiB
C
155 lines
6.4 KiB
C
/** @file
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* Header defining Versatile Express constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __ARM_VEXPRESS_CTA15A7_H__
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#define __ARM_VEXPRESS_CTA15A7_H__
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#include <VExpressMotherBoard.h>
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/***********************************************************************************
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// Platform Memory Map
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************************************************************************************/
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
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#ifdef ARM_BIGLITTLE_TC2
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// Secure NOR Flash
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#define ARM_VE_SEC_NOR0_BASE 0x00000000
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#define ARM_VE_SEC_NOR0_SZ SIZE_64MB
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// Secure RAM
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#define ARM_VE_SEC_RAM0_BASE 0x04000000
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#define ARM_VE_SEC_RAM0_SZ SIZE_64MB
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#endif
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// NOR Flash 0
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#define ARM_VE_SMB_NOR0_BASE 0x08000000
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#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
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// NOR Flash 1
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#define ARM_VE_SMB_NOR1_BASE 0x0C000000
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#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
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// SRAM
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#define ARM_VE_SMB_SRAM_BASE 0x14000000
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#define ARM_VE_SMB_SRAM_SZ SIZE_32MB
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// USB, Ethernet, VRAM
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#ifdef ARM_BIGLITTLE_TC2
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#define ARM_VE_SMB_PERIPH_BASE 0x18000000
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#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZE_16MB)
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#else
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#define ARM_VE_SMB_PERIPH_BASE 0x1C000000
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#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB)
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#endif
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#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
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// On-Chip non-secure ROM
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#ifdef ARM_BIGLITTLE_TC2
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#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000
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#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB
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#endif
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// On-Chip Peripherals
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#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000
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#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000
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// On-Chip non-secure SRAM
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#ifdef ARM_BIGLITTLE_TC2
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#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000
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#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB
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#endif
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// Allocate a section for the VRAM (Video RAM)
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// If 0 then allow random memory allocation
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#define LCD_VRAM_CORE_TILE_BASE 0
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// Define SEC phase sync point
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#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)
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/***********************************************************************************
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Core Tile memory-mapped Peripherals
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************************************************************************************/
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// PL354 Static Memory Controller Base
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#ifdef ARM_BIGLITTLE_TC2
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#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000
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#else
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#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
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#endif
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#define ARM_CTA15A7_SCC_BASE 0x7FFF0000
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#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x700)
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#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48
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#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)
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#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)
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#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)
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#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)
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#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH (1 << 4)
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#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x3C)
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#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x68)
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#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x6C)
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#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x70)
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#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x74)
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#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x78)
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#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x7C)
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#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x80)
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#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x84)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8)
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#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5)
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#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6)
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/***********************************************************************************
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// Memory-mapped peripherals
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************************************************************************************/
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/*// SP810 Controller
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#undef SP810_CTRL_BASE
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#define SP810_CTRL_BASE 0x1C020000
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// PL111 Colour LCD Controller
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#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
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#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
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#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
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// VRAM offset for the PL111 Colour LCD Controller on the motherboard
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#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)*/
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#endif
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