mirror of https://github.com/acidanthera/audk.git
188 lines
5.8 KiB
C
188 lines
5.8 KiB
C
/*++
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Copyright (c) 2006, Intel Corporation. All rights reserved.
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This software and associated documentation (if any) is furnished
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under a license and may only be used or copied in accordance
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with the terms of the license. Except as permitted by such
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license, no part of this software or documentation may be
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reproduced, stored in a retrieval system, or transmitted in any
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form or by any means without the express written consent of
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Intel Corporation.
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Module Name:
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CpuIA32.h
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Abstract:
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Basic Definition for IA32 Architecture.
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--*/
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#ifndef _CPU_IA32_H_
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#define _CPU_IA32_H_
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typedef struct {
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UINT32 RegEax;
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UINT32 RegEbx;
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UINT32 RegEcx;
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UINT32 RegEdx;
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} EFI_CPUID_REGISTER;
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#pragma pack(1)
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//
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// Definition for IA32 microcode format
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//
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typedef struct {
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UINT32 HeaderVersion;
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UINT32 UpdateRevision;
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UINT32 Date;
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UINT32 ProcessorId;
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UINT32 Checksum;
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UINT32 LoaderRevision;
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UINT32 ProcessorFlags;
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UINT32 DataSize;
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UINT32 TotalSize;
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UINT8 Reserved[12];
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} EFI_CPU_MICROCODE_HEADER;
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typedef struct {
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UINT32 ExtendedSignatureCount;
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UINT32 ExtendedTableChecksum;
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UINT8 Reserved[12];
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} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
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typedef struct {
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UINT32 ProcessorSignature;
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UINT32 ProcessorFlag;
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UINT32 ProcessorChecksum;
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} EFI_CPU_MICROCODE_EXTENDED_TABLE;
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//
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// The MS compiler doesn't handle QWORDs very well. So break
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// them into DWORDs to circumvent the problem.
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//
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typedef union _MSR_REGISTER {
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UINT64 Qword;
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struct _DWORDS {
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UINT32 Low;
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UINT32 High;
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} Dwords;
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struct _BYTES {
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UINT8 FirstByte;
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UINT8 SecondByte;
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UINT8 ThirdByte;
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UINT8 FouthByte;
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UINT8 FifthByte;
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UINT8 SixthByte;
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UINT8 SeventhByte;
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UINT8 EighthByte;
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} Bytes;
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} MSR_REGISTER;
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#pragma pack()
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//
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// Definition for CPUID Index
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//
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#define EFI_CPUID_SIGNATURE 0x0
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#define EFI_CPUID_VERSION_INFO 0x1
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#define EFI_CPUID_CACHE_INFO 0x2
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#define EFI_CPUID_SERIAL_NUMBER 0x3
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#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
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#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
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#define EFI_CPUID_BRAND_STRING1 0x80000002
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#define EFI_CPUID_BRAND_STRING2 0x80000003
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#define EFI_CPUID_BRAND_STRING3 0x80000004
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#define EFI_CPUID_ADDRESS_SIZE 0x80000008
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//
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// Definition for MSR address
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//
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#define EFI_MSR_IA32_PLATFORM_ID 0x17
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#define EFI_MSR_IA32_APIC_BASE 0x1B
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#define EFI_MSR_EBC_HARD_POWERON 0x2A
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#define EFI_MSR_EBC_SOFT_POWERON 0x2B
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#define EFI_MSR_EBC_FREQUENCY_ID 0x2C
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#define MSR_IA32_FEATURE_CONTROL 0x3A
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#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
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#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
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#define EFI_MSR_PSB_CLOCK_STATUS 0xCD
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#define MSR_EXT_CONFIG 0xEE
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#define EFI_IA32_MCG_CAP 0x179
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#define EFI_IA32_MCG_CTL 0x17B
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#define EFI_MSR_IA32_PERF_STS 0x198
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#define EFI_MSR_IA32_PERF_CTL 0x199
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#define EFI_MSR_IA32_CLOCK_MODULATION 0x19A
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#define MSR_IA32_THERMAL_INTERRUPT 0x19B
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#define EFI_MSR_IA32_THERM_STATUS 0x19C
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#define EFI_MSR_GV_THERM 0x19D
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#define MSR_IA32_MISC_ENABLE 0x1A0
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#define MSR_PIC_SENS_CFG 0x1AA
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#define EFI_IA32_MC0_CTL 0x400
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#define EFI_IA32_MC0_STATUS 0x401
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#define MSR_PECI_CONTROL 0x5A0
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//
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// Definition for MTRR address and related values
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//
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#define EFI_IA32_MTRR_FIX64K_00000 0x250
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#define EFI_IA32_MTRR_FIX16K_80000 0x258
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#define EFI_IA32_MTRR_FIX16K_A0000 0x259
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#define EFI_IA32_MTRR_FIX4K_C0000 0x268
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#define EFI_IA32_MTRR_FIX4K_C8000 0x269
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#define EFI_IA32_MTRR_FIX4K_D0000 0x26A
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#define EFI_IA32_MTRR_FIX4K_D8000 0x26B
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#define EFI_IA32_MTRR_FIX4K_E0000 0x26C
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#define EFI_IA32_MTRR_FIX4K_E8000 0x26D
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#define EFI_IA32_MTRR_FIX4K_F0000 0x26E
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#define EFI_IA32_MTRR_FIX4K_F8000 0x26F
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#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
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#define EFI_CACHE_VARIABLE_MTRR_END 0x20F
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#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
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#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
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#define EFI_MSR_VALID_MASK 0xFFFFFFFFF
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#define EFI_CACHE_MTRR_VALID 0x800
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#define EFI_CACHE_FIXED_MTRR_VALID 0x400
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#define EFI_CACHE_UNCACHEABLE 0
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#define EFI_CACHE_WRITECOMBINING 1
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#define EFI_CACHE_WRITETHROUGH 4
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#define EFI_CACHE_WRITEPROTECTED 5
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#define EFI_CACHE_WRITEBACK 6
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//
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// Definition for Local APIC registers and related values
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//
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#define LOCAL_APIC_LVT_TIMER 0x320
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#define LOCAL_APIC_TIMER_INIT_COUNT 0x380
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#define LOCAL_APIC_TIMER_COUNT 0x390
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#define LOCAL_APIC_TIMER_DIVIDE 0x3E0
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#define DELIVERY_MODE_FIXED 0x0
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#define DELIVERY_MODE_LOWEST_PRIORITY 0x1
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#define DELIVERY_MODE_SMI 0x2
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#define DELIVERY_MODE_REMOTE_READ 0x3
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#define DELIVERY_MODE_NMI 0x4
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#define DELIVERY_MODE_INIT 0x5
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#define DELIVERY_MODE_SIPI 0x6
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#define TRIGGER_MODE_EDGE 0x0
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#define TRIGGER_MODE_LEVEL 0x1
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//
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// CPU System Memory Map Definition
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//
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#define CPU_MSI_MEMORY_BASE 0xFEE00000
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#define CPU_MSI_MEMORY_SIZE 0x100000
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#endif
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