mirror of https://github.com/acidanthera/audk.git
172 lines
4.3 KiB
C
172 lines
4.3 KiB
C
/** @file
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This file contains the platform independent parts of PL111Lcd
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Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/LcdHwLib.h>
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#include <Library/LcdPlatformLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include "PL111Lcd.h"
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/** Check for presence of PL111.
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@retval EFI_SUCCESS Returns success if platform implements a
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PL111 controller.
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@retval EFI_NOT_FOUND PL111 display controller not found the plaform.
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**/
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EFI_STATUS
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LcdIdentify (
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VOID
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)
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{
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DEBUG ((
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DEBUG_WARN,
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"Probing ID registers at 0x%lx for a PL111\n",
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PL111_REG_CLCD_PERIPH_ID_0
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));
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// Check if this is a PL111
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if ((MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0) &&
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(MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1) &&
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((MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2) &&
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(MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3) &&
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(MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0) &&
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(MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1) &&
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(MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2) &&
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(MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3))
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{
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return EFI_SUCCESS;
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}
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return EFI_NOT_FOUND;
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}
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/** Initialize display.
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@param[in] VramBaseAddress Address of the framebuffer.
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@retval EFI_SUCCESS Initialization of display successful.
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**/
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EFI_STATUS
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LcdInitialize (
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IN EFI_PHYSICAL_ADDRESS VramBaseAddress
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)
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{
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// Define start of the VRAM. This never changes for any graphics mode
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MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress);
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MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
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// Disable all interrupts from the PL111
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MmioWrite32 (PL111_REG_LCD_IMSC, 0);
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return EFI_SUCCESS;
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}
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/** Set requested mode of the display.
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@param[in] ModeNumbe Display mode number.
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@retval EFI_SUCCESS Display mode set successfuly.
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@retval !(EFI_SUCCESS) Other errors.
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**/
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EFI_STATUS
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LcdSetMode (
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IN UINT32 ModeNumber
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)
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{
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EFI_STATUS Status;
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SCAN_TIMINGS *Horizontal;
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SCAN_TIMINGS *Vertical;
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UINT32 LcdControl;
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LCD_BPP LcdBpp;
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EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;
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// Set the video mode timings and other relevant information
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Status = LcdPlatformGetTimings (
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ModeNumber,
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&Horizontal,
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&Vertical
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);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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ASSERT (Horizontal != NULL);
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ASSERT (Vertical != NULL);
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Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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// Get the pixel format information
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Status = LcdPlatformQueryMode (ModeNumber, &ModeInfo);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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// Disable the CLCD_LcdEn bit
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MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);
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// Set Timings
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MmioWrite32 (
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PL111_REG_LCD_TIMING_0,
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HOR_AXIS_PANEL (
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Horizontal->BackPorch,
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Horizontal->FrontPorch,
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Horizontal->Sync,
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Horizontal->Resolution
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)
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);
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MmioWrite32 (
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PL111_REG_LCD_TIMING_1,
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VER_AXIS_PANEL (
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Vertical->BackPorch,
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Vertical->FrontPorch,
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Vertical->Sync,
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Vertical->Resolution
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)
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);
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MmioWrite32 (
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PL111_REG_LCD_TIMING_2,
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CLK_SIG_POLARITY (Horizontal->Resolution)
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);
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MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);
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// PL111_REG_LCD_CONTROL
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LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) |
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PL111_CTRL_LCD_TFT | PL111_CTRL_LCD_PWR;
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if (ModeInfo.PixelFormat == PixelBlueGreenRedReserved8BitPerColor) {
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LcdControl |= PL111_CTRL_BGR;
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}
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MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
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return EFI_SUCCESS;
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}
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/** De-initializes the display.
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*/
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VOID
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LcdShutdown (
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VOID
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)
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{
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// Disable the controller
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MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);
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}
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