mirror of https://github.com/acidanthera/audk.git
934 lines
31 KiB
C
934 lines
31 KiB
C
/** @file
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PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PchSpi.h"
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VOID
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FillOutPublicInfoStruct (
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SPI_INSTANCE *SpiInstance
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)
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/*++
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Routine Description:
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Fillout SpiInstance->InitInfo;
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Arguments:
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SpiInstance - Pointer to SpiInstance to initialize
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Returns:
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NONE
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--*/
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{
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UINT8 Index;
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SpiInstance->InitInfo.InitTable = &SpiInstance->SpiInitTable;
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//
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// Give invalid index in case operation not supported.
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//
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SpiInstance->InitInfo.JedecIdOpcodeIndex = 0xff;
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SpiInstance->InitInfo.OtherOpcodeIndex = 0xff;
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SpiInstance->InitInfo.WriteStatusOpcodeIndex = 0xff;
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SpiInstance->InitInfo.ProgramOpcodeIndex = 0xff;
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SpiInstance->InitInfo.ReadOpcodeIndex = 0xff;
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SpiInstance->InitInfo.EraseOpcodeIndex = 0xff;
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SpiInstance->InitInfo.ReadStatusOpcodeIndex = 0xff;
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SpiInstance->InitInfo.FullChipEraseOpcodeIndex = 0xff;
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for (Index = 0; Index < SPI_NUM_OPCODE; Index++) {
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationJedecId) {
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SpiInstance->InitInfo.JedecIdOpcodeIndex = Index;
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationOther) {
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SpiInstance->InitInfo.OtherOpcodeIndex = Index;
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationWriteStatus) {
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SpiInstance->InitInfo.WriteStatusOpcodeIndex = Index;
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationProgramData_1_Byte ||
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SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationProgramData_64_Byte) {
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SpiInstance->InitInfo.ProgramOpcodeIndex = Index;
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationReadData ||
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SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationFastRead ||
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SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationDualOutputFastRead) {
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SpiInstance->InitInfo.ReadOpcodeIndex = Index;
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_256_Byte ||
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SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_4K_Byte ||
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SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_8K_Byte ||
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SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationErase_64K_Byte) {
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SpiInstance->InitInfo.EraseOpcodeIndex = Index;
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationReadStatus) {
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SpiInstance->InitInfo.ReadStatusOpcodeIndex = Index;
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationFullChipErase) {
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SpiInstance->InitInfo.FullChipEraseOpcodeIndex = Index;
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}
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}
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}
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EFI_STATUS
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SpiProtocolConstructor (
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SPI_INSTANCE *SpiInstance
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)
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/*++
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Routine Description:
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Initialize an SPI protocol instance.
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The function will assert in debug if PCH RCBA has not been initialized
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Arguments:
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SpiInstance - Pointer to SpiInstance to initialize
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Returns:
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EFI_SUCCESS The protocol instance was properly initialized
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EFI_UNSUPPORTED The PCH is not supported by this module
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--*/
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{
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SpiInstance->InitDone = FALSE; // Indicate NOT READY.
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//
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// Check if the current PCH is known and supported by this code
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//
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if (!IsQncSupported ()) {
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DEBUG ((DEBUG_ERROR, "PCH SPI Protocol not supported due to no proper QNC LPC found!\n"));
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return EFI_UNSUPPORTED;
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}
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//
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// Initialize the SPI protocol instance
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//
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SpiInstance->Signature = PCH_SPI_PRIVATE_DATA_SIGNATURE;
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SpiInstance->Handle = NULL;
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SpiInstance->SpiProtocol.Init = SpiProtocolInit;
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SpiInstance->SpiProtocol.Lock = SpiProtocolLock;
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SpiInstance->SpiProtocol.Execute = SpiProtocolExecute;
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SpiInstance->SpiProtocol.Info = SpiProtocolInfo;
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//
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// Sanity check to ensure PCH RCBA initialization has occurred previously.
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//
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SpiInstance->PchRootComplexBar = MmioRead32 (
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PciDeviceMmBase (PCI_BUS_NUMBER_QNC,
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PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC) + R_QNC_LPC_RCBA
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) & B_QNC_LPC_RCBA_MASK;
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ASSERT (SpiInstance->PchRootComplexBar != 0);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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UnlockFlashComponents (
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IN EFI_SPI_PROTOCOL *This,
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IN UINT8 UnlockCmdOpcodeIndex
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)
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/*++
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Routine Description:
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Issue unlock command to disable block protection, this only needs to be done once per SPI power on
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Arguments:
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This A pointer to "EFI_SPI_PROTOCOL" for issuing commands
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UnlockCmdOpcodeIndex The index of the Unlock command
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Returns:
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EFI_SUCCESS UnLock operation succeed.
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EFI_DEVICE_ERROR Device error, operation failed.
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--*/
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{
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EFI_STATUS Status;
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SPI_INSTANCE *SpiInstance;
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UINT8 SpiStatus;
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if (UnlockCmdOpcodeIndex >= SPI_NUM_OPCODE) {
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return EFI_UNSUPPORTED;
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}
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SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
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//
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// Issue unlock command to disable block protection, this only needs to be done once per SPI power on
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//
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SpiStatus = 0;
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//
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// Issue unlock command to the flash component 1 at first
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//
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Status = SpiProtocolExecute (
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This,
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UnlockCmdOpcodeIndex,
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SpiInstance->SpiInitTable.PrefixOpcode[0] == PCH_SPI_COMMAND_WRITE_ENABLE ? 0 : 1,
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TRUE,
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TRUE,
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TRUE,
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(UINTN) 0,
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sizeof (SpiStatus),
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&SpiStatus,
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EnumSpiRegionAll
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "Unlock flash component 1 fail!\n"));
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return Status;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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SpiProtocolInit (
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IN EFI_SPI_PROTOCOL *This,
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IN SPI_INIT_TABLE *InitTable
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)
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/*++
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Routine Description:
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Initialize the host controller to execute SPI command.
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Arguments:
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This Pointer to the EFI_SPI_PROTOCOL instance.
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InitTable Initialization data to be programmed into the SPI host controller.
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Returns:
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EFI_SUCCESS Initialization completed.
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EFI_ACCESS_DENIED The SPI static configuration interface has been locked-down.
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EFI_INVALID_PARAMETER Bad input parameters.
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EFI_UNSUPPORTED Can't get Descriptor mode VSCC values
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--*/
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{
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EFI_STATUS Status;
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UINT8 Index;
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UINT16 OpcodeType;
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SPI_INSTANCE *SpiInstance;
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UINTN PchRootComplexBar;
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UINT8 UnlockCmdOpcodeIndex;
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UINT8 FlashPartId[3];
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SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
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PchRootComplexBar = SpiInstance->PchRootComplexBar;
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if (InitTable != NULL) {
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//
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// Copy table into SPI driver Private data structure
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//
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CopyMem (
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&SpiInstance->SpiInitTable,
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InitTable,
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sizeof (SPI_INIT_TABLE)
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);
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} else {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Check if the SPI interface has been locked-down.
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//
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if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {
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ASSERT_EFI_ERROR (EFI_ACCESS_DENIED);
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return EFI_ACCESS_DENIED;
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}
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//
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// Clear all the status bits for status regs.
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//
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MmioOr16 (
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(UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS),
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(UINT16) ((B_QNC_RCRB_SPIS_CDS | B_QNC_RCRB_SPIS_BAS))
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);
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MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS);
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//
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// Set the Prefix Opcode registers.
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//
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MmioWrite16 (
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PchRootComplexBar + R_QNC_RCRB_SPIPREOP,
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(SpiInstance->SpiInitTable.PrefixOpcode[1] << 8) | InitTable->PrefixOpcode[0]
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);
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MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIPREOP);
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//
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// Set Opcode Type Configuration registers.
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//
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for (Index = 0, OpcodeType = 0; Index < SPI_NUM_OPCODE; Index++) {
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switch (SpiInstance->SpiInitTable.OpcodeMenu[Index].Type) {
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case EnumSpiOpcodeRead:
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OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_ADD_READ << (Index * 2));
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break;
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case EnumSpiOpcodeWrite:
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OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_ADD_WRITE << (Index * 2));
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break;
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case EnumSpiOpcodeWriteNoAddr:
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OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE << (Index * 2));
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break;
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default:
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OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_NOADD_READ << (Index * 2));
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break;
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}
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}
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MmioWrite16 (PchRootComplexBar + R_QNC_RCRB_SPIOPTYPE, OpcodeType);
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MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIOPTYPE);
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//
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// Setup the Opcode Menu registers.
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//
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UnlockCmdOpcodeIndex = SPI_NUM_OPCODE;
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for (Index = 0; Index < SPI_NUM_OPCODE; Index++) {
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MmioWrite8 (
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PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + Index,
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SpiInstance->SpiInitTable.OpcodeMenu[Index].Code
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);
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MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + Index);
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationJedecId) {
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Status = SpiProtocolExecute (
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This,
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Index,
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0,
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TRUE,
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TRUE,
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FALSE,
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(UINTN) 0,
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3,
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FlashPartId,
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EnumSpiRegionDescriptor
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (FlashPartId[0] != SpiInstance->SpiInitTable.VendorId ||
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FlashPartId[1] != SpiInstance->SpiInitTable.DeviceId0 ||
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FlashPartId[2] != SpiInstance->SpiInitTable.DeviceId1) {
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return EFI_INVALID_PARAMETER;
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}
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}
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if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationWriteStatus) {
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UnlockCmdOpcodeIndex = Index;
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}
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}
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Status = UnlockFlashComponents (
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This,
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UnlockCmdOpcodeIndex
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "Unlock flash components fail!\n"));
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}
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SpiPhaseInit ();
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FillOutPublicInfoStruct (SpiInstance);
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SpiInstance->InitDone = TRUE;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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SpiProtocolLock (
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IN EFI_SPI_PROTOCOL *This
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)
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/*++
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Routine Description:
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Lock the SPI Static Configuration Interface.
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Once locked, the interface can not be changed and can only be clear by system reset.
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Arguments:
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This Pointer to the EFI_SPI_PROTOCOL instance.
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Returns:
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EFI_SUCCESS Lock operation succeed.
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EFI_DEVICE_ERROR Device error, operation failed.
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EFI_ACCESS_DENIED The interface has already been locked.
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--*/
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{
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SPI_INSTANCE *SpiInstance;
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UINTN PchRootComplexBar;
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SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
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PchRootComplexBar = SpiInstance->PchRootComplexBar;
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//
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// Check if the SPI interface has been locked-down.
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//
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if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {
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return EFI_ACCESS_DENIED;
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}
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//
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// Lock-down the configuration interface.
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//
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MmioOr16 ((UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS), (UINT16) (B_QNC_RCRB_SPIS_SCL));
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//
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// Verify if it's really locked.
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//
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if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) == 0) {
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return EFI_DEVICE_ERROR;
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} else {
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//
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// Save updated register in S3 Boot script.
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//
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint16,
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(UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS),
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1,
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(VOID *) (UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS)
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);
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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SpiProtocolExecute (
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IN EFI_SPI_PROTOCOL *This,
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IN UINT8 OpcodeIndex,
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IN UINT8 PrefixOpcodeIndex,
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IN BOOLEAN DataCycle,
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IN BOOLEAN Atomic,
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IN BOOLEAN ShiftOut,
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IN UINTN Address,
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IN UINT32 DataByteCount,
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IN OUT UINT8 *Buffer,
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IN SPI_REGION_TYPE SpiRegionType
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)
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/*++
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Routine Description:
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Execute SPI commands from the host controller.
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This function would be called by runtime driver, please do not use any MMIO marco here
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Arguments:
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This Pointer to the EFI_SPI_PROTOCOL instance.
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OpcodeIndex Index of the command in the OpCode Menu.
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PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.
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DataCycle TRUE if the SPI cycle contains data
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Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.
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ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.
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Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform
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Region, this value specifies the offset from the Region Base; for BIOS Region,
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this value specifies the offset from the start of the BIOS Image. In Non
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Descriptor Mode, this value specifies the offset from the start of the BIOS Image.
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Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor
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Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is
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supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or
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the flash (in Non Descriptor Mode)
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DataByteCount Number of bytes in the data portion of the SPI cycle. This function may break the
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data transfer into multiple operations. This function ensures each operation does
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not cross 256 byte flash address boundary.
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*NOTE: if there is some SPI chip that has a stricter address boundary requirement
|
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(e.g., its write page size is < 256 byte), then the caller cannot rely on this
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function to cut the data transfer at proper address boundaries, and it's the
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caller's reponsibility to pass in a properly cut DataByteCount parameter.
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Buffer Pointer to caller-allocated buffer containing the dada received or sent during the
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SPI cycle.
|
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SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,
|
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EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in
|
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Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode
|
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and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative
|
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to base of the 1st flash device (i.e., it is a Flash Linear Address).
|
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|
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Returns:
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EFI_SUCCESS Command succeed.
|
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EFI_INVALID_PARAMETER The parameters specified are not valid.
|
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EFI_UNSUPPORTED Command not supported.
|
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EFI_DEVICE_ERROR Device error, command aborts abnormally.
|
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|
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--*/
|
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{
|
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EFI_STATUS Status;
|
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UINT16 BiosCtlSave;
|
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UINT32 SmiEnSave;
|
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|
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BiosCtlSave = 0;
|
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SmiEnSave = 0;
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|
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//
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// Check if the parameters are valid.
|
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//
|
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if ((OpcodeIndex >= SPI_NUM_OPCODE) || (PrefixOpcodeIndex >= SPI_NUM_PREFIX_OPCODE)) {
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return EFI_INVALID_PARAMETER;
|
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}
|
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//
|
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// Make sure it's safe to program the command.
|
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//
|
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if (!WaitForSpiCycleComplete (This, FALSE)) {
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return EFI_DEVICE_ERROR;
|
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}
|
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|
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//
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// Acquire access to the SPI interface is not required any more.
|
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//
|
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//
|
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// Disable SMIs to make sure normal mode flash access is not interrupted by an SMI
|
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// whose SMI handler accesses flash (e.g. for error logging)
|
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//
|
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SmiEnSave = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
|
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, (SmiEnSave & ~SMI_EN));
|
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|
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//
|
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// Save BIOS Ctrl register
|
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//
|
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BiosCtlSave = PciRead16 (
|
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PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,
|
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PCI_DEVICE_NUMBER_QNC_LPC,
|
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PCI_FUNCTION_NUMBER_QNC_LPC,
|
|
R_QNC_LPC_BIOS_CNTL)
|
|
) & (B_QNC_LPC_BIOS_CNTL_BCD | B_QNC_LPC_BIOS_CNTL_PFE | B_QNC_LPC_BIOS_CNTL_BIOSWE | B_QNC_LPC_BIOS_CNTL_SMM_BWP);
|
|
|
|
//
|
|
// Enable flash writing
|
|
//
|
|
PciOr16 (
|
|
PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,
|
|
PCI_DEVICE_NUMBER_QNC_LPC,
|
|
PCI_FUNCTION_NUMBER_QNC_LPC,
|
|
R_QNC_LPC_BIOS_CNTL),
|
|
(UINT16) (B_QNC_LPC_BIOS_CNTL_BIOSWE | B_QNC_LPC_BIOS_CNTL_SMM_BWP)
|
|
);
|
|
|
|
//
|
|
// If shifts the data out, disable Prefetching and Caching.
|
|
//
|
|
if (ShiftOut) {
|
|
PciAndThenOr16 (
|
|
PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,
|
|
PCI_DEVICE_NUMBER_QNC_LPC,
|
|
PCI_FUNCTION_NUMBER_QNC_LPC,
|
|
R_QNC_LPC_BIOS_CNTL),
|
|
(UINT16) (~(B_QNC_LPC_BIOS_CNTL_BCD | B_QNC_LPC_BIOS_CNTL_PFE)),
|
|
(UINT16) ((B_QNC_LPC_BIOS_CNTL_BCD))
|
|
);
|
|
}
|
|
//
|
|
// Sends the command to the SPI interface to execute.
|
|
//
|
|
Status = SendSpiCmd (
|
|
This,
|
|
OpcodeIndex,
|
|
PrefixOpcodeIndex,
|
|
DataCycle,
|
|
Atomic,
|
|
ShiftOut,
|
|
Address,
|
|
DataByteCount,
|
|
Buffer,
|
|
SpiRegionType
|
|
);
|
|
|
|
//
|
|
// Restore BIOS Ctrl register
|
|
//
|
|
PciAndThenOr16 (
|
|
PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC,
|
|
PCI_DEVICE_NUMBER_QNC_LPC,
|
|
PCI_FUNCTION_NUMBER_QNC_LPC,
|
|
R_QNC_LPC_BIOS_CNTL),
|
|
(UINT16) (~(B_QNC_LPC_BIOS_CNTL_BCD | B_QNC_LPC_BIOS_CNTL_PFE | B_QNC_LPC_BIOS_CNTL_BIOSWE | B_QNC_LPC_BIOS_CNTL_SMM_BWP)),
|
|
(UINT16) (BiosCtlSave)
|
|
);
|
|
//
|
|
// Restore SMIs.
|
|
//
|
|
QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, SmiEnSave);
|
|
|
|
return Status;
|
|
}
|
|
|
|
VOID
|
|
SpiOffset2Physical (
|
|
IN EFI_SPI_PROTOCOL *This,
|
|
IN UINTN SpiRegionOffset,
|
|
IN SPI_REGION_TYPE SpiRegionType,
|
|
OUT UINTN *HardwareSpiAddress,
|
|
OUT UINTN *BaseAddress,
|
|
OUT UINTN *LimitAddress
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Convert SPI offset to Physical address of SPI hardware
|
|
|
|
Arguments:
|
|
|
|
This Pointer to the EFI_SPI_PROTOCOL instance.
|
|
SpiRegionOffset In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform
|
|
Region, this value specifies the offset from the Region Base; for BIOS Region,
|
|
this value specifies the offset from the start of the BIOS Image. In Non
|
|
Descriptor Mode, this value specifies the offset from the start of the BIOS Image.
|
|
Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor
|
|
Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is
|
|
supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or
|
|
the flash (in Non Descriptor Mode)
|
|
BaseAddress Base Address of the region.
|
|
SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,
|
|
EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in
|
|
Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode
|
|
and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative
|
|
to base of the 1st flash device (i.e., it is a Flash Linear Address).
|
|
HardwareSpiAddress Return absolution SPI address (i.e., Flash Linear Address)
|
|
BaseAddress Return base address of the region type
|
|
LimitAddress Return limit address of the region type
|
|
|
|
Returns:
|
|
|
|
EFI_SUCCESS Command succeed.
|
|
|
|
--*/
|
|
{
|
|
SPI_INSTANCE *SpiInstance;
|
|
|
|
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
|
|
|
|
if (SpiRegionType == EnumSpiRegionAll) {
|
|
//
|
|
// EnumSpiRegionAll indicates address is relative to flash device (i.e., address is Flash
|
|
// Linear Address)
|
|
//
|
|
*HardwareSpiAddress = SpiRegionOffset;
|
|
} else {
|
|
//
|
|
// Otherwise address is relative to BIOS image
|
|
//
|
|
*HardwareSpiAddress = SpiRegionOffset + SpiInstance->SpiInitTable.BiosStartOffset;
|
|
}
|
|
}
|
|
|
|
EFI_STATUS
|
|
SendSpiCmd (
|
|
IN EFI_SPI_PROTOCOL *This,
|
|
IN UINT8 OpcodeIndex,
|
|
IN UINT8 PrefixOpcodeIndex,
|
|
IN BOOLEAN DataCycle,
|
|
IN BOOLEAN Atomic,
|
|
IN BOOLEAN ShiftOut,
|
|
IN UINTN Address,
|
|
IN UINT32 DataByteCount,
|
|
IN OUT UINT8 *Buffer,
|
|
IN SPI_REGION_TYPE SpiRegionType
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function sends the programmed SPI command to the slave device.
|
|
|
|
Arguments:
|
|
|
|
OpcodeIndex Index of the command in the OpCode Menu.
|
|
PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.
|
|
DataCycle TRUE if the SPI cycle contains data
|
|
Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.
|
|
ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.
|
|
Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform
|
|
Region, this value specifies the offset from the Region Base; for BIOS Region,
|
|
this value specifies the offset from the start of the BIOS Image. In Non
|
|
Descriptor Mode, this value specifies the offset from the start of the BIOS Image.
|
|
Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor
|
|
Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is
|
|
supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or
|
|
the flash (in Non Descriptor Mode)
|
|
DataByteCount Number of bytes in the data portion of the SPI cycle. This function may break the
|
|
data transfer into multiple operations. This function ensures each operation does
|
|
not cross 256 byte flash address boundary.
|
|
*NOTE: if there is some SPI chip that has a stricter address boundary requirement
|
|
(e.g., its write page size is < 256 byte), then the caller cannot rely on this
|
|
function to cut the data transfer at proper address boundaries, and it's the
|
|
caller's reponsibility to pass in a properly cut DataByteCount parameter.
|
|
Buffer Data received or sent during the SPI cycle.
|
|
SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,
|
|
EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in
|
|
Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode
|
|
and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative
|
|
to base of the 1st flash device (i.e., it is a Flash Linear Address).
|
|
|
|
Returns:
|
|
|
|
EFI_SUCCESS SPI command completes successfully.
|
|
EFI_DEVICE_ERROR Device error, the command aborts abnormally.
|
|
EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
|
|
EFI_INVALID_PARAMETER The parameters specified are not valid.
|
|
|
|
--*/
|
|
{
|
|
UINT32 Index;
|
|
SPI_INSTANCE *SpiInstance;
|
|
UINTN HardwareSpiAddr;
|
|
UINTN SpiBiosSize;
|
|
UINTN BaseAddress;
|
|
UINTN LimitAddress;
|
|
UINT32 SpiDataCount;
|
|
UINT8 OpCode;
|
|
UINTN PchRootComplexBar;
|
|
|
|
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
|
|
PchRootComplexBar = SpiInstance->PchRootComplexBar;
|
|
SpiBiosSize = SpiInstance->SpiInitTable.BiosSize;
|
|
OpCode = MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + OpcodeIndex);
|
|
|
|
//
|
|
// Check if the value of opcode register is 0 or the BIOS Size of SpiInitTable is 0
|
|
//
|
|
if (OpCode == 0 || SpiBiosSize == 0) {
|
|
ASSERT (FALSE);
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
SpiOffset2Physical (This, Address, SpiRegionType, &HardwareSpiAddr, &BaseAddress, &LimitAddress);
|
|
//
|
|
// Have direct access to BIOS region in Descriptor mode,
|
|
//
|
|
if (SpiInstance->SpiInitTable.OpcodeMenu[OpcodeIndex].Type == EnumSpiOpcodeRead &&
|
|
SpiRegionType == EnumSpiRegionBios) {
|
|
CopyMem (
|
|
Buffer,
|
|
(UINT8 *) ((HardwareSpiAddr - BaseAddress) + (UINT32) (~(SpiBiosSize - 1))),
|
|
DataByteCount
|
|
);
|
|
return EFI_SUCCESS;
|
|
}
|
|
//
|
|
// DEBUG((EFI_D_ERROR, "SPIADDR %x, %x, %x, %x\n", Address, HardwareSpiAddr, BaseAddress,
|
|
// LimitAddress));
|
|
//
|
|
if ((DataCycle == FALSE) && (DataByteCount > 0)) {
|
|
DataByteCount = 0;
|
|
}
|
|
|
|
do {
|
|
//
|
|
// Trim at 256 byte boundary per operation,
|
|
// - PCH SPI controller requires trimming at 4KB boundary
|
|
// - Some SPI chips require trimming at 256 byte boundary for write operation
|
|
// - Trimming has limited performance impact as we can read / write atmost 64 byte
|
|
// per operation
|
|
//
|
|
if (HardwareSpiAddr + DataByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
|
|
SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
|
|
} else {
|
|
SpiDataCount = DataByteCount;
|
|
}
|
|
//
|
|
// Calculate the number of bytes to shift in/out during the SPI data cycle.
|
|
// Valid settings for the number of bytes duing each data portion of the
|
|
// PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
|
|
//
|
|
if (SpiDataCount >= 64) {
|
|
SpiDataCount = 64;
|
|
} else if ((SpiDataCount &~0x07) != 0) {
|
|
SpiDataCount = SpiDataCount &~0x07;
|
|
}
|
|
//
|
|
// If shifts data out, load data into the SPI data buffer.
|
|
//
|
|
if (ShiftOut) {
|
|
for (Index = 0; Index < SpiDataCount; Index++) {
|
|
MmioWrite8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index, Buffer[Index]);
|
|
MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index);
|
|
}
|
|
}
|
|
|
|
MmioWrite32 (
|
|
(PchRootComplexBar + R_QNC_RCRB_SPIA),
|
|
(UINT32) (HardwareSpiAddr & B_QNC_RCRB_SPIA_MASK)
|
|
);
|
|
MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIA);
|
|
|
|
//
|
|
// Execute the command on the SPI compatible mode
|
|
//
|
|
|
|
//
|
|
// Clear error flags
|
|
//
|
|
MmioOr16 ((PchRootComplexBar + R_QNC_RCRB_SPIS), B_QNC_RCRB_SPIS_BAS);
|
|
|
|
//
|
|
// Initialte the SPI cycle
|
|
//
|
|
if (DataCycle) {
|
|
MmioWrite16 (
|
|
(PchRootComplexBar + R_QNC_RCRB_SPIC),
|
|
( (UINT16) (B_QNC_RCRB_SPIC_DC) | (UINT16) (((SpiDataCount - 1) << 8) & B_QNC_RCRB_SPIC_DBC) |
|
|
(UINT16) ((OpcodeIndex << 4) & B_QNC_RCRB_SPIC_COP) |
|
|
(UINT16) ((PrefixOpcodeIndex << 3) & B_QNC_RCRB_SPIC_SPOP) |
|
|
(UINT16) (Atomic ? B_QNC_RCRB_SPIC_ACS : 0) |
|
|
(UINT16) (B_QNC_RCRB_SPIC_SCGO)));
|
|
} else {
|
|
MmioWrite16 (
|
|
(PchRootComplexBar + R_QNC_RCRB_SPIC),
|
|
( (UINT16) ((OpcodeIndex << 4) & B_QNC_RCRB_SPIC_COP) |
|
|
(UINT16) ((PrefixOpcodeIndex << 3) & B_QNC_RCRB_SPIC_SPOP) |
|
|
(UINT16) (Atomic ? B_QNC_RCRB_SPIC_ACS : 0) |
|
|
(UINT16) (B_QNC_RCRB_SPIC_SCGO)));
|
|
}
|
|
|
|
MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIC);
|
|
|
|
//
|
|
// end of command execution
|
|
//
|
|
// Wait the SPI cycle to complete.
|
|
//
|
|
if (!WaitForSpiCycleComplete (This, TRUE)) {
|
|
return EFI_DEVICE_ERROR;
|
|
}
|
|
//
|
|
// If shifts data in, get data from the SPI data buffer.
|
|
//
|
|
if (!ShiftOut) {
|
|
for (Index = 0; Index < SpiDataCount; Index++) {
|
|
Buffer[Index] = MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index);
|
|
}
|
|
}
|
|
|
|
HardwareSpiAddr += SpiDataCount;
|
|
Buffer += SpiDataCount;
|
|
DataByteCount -= SpiDataCount;
|
|
} while (DataByteCount > 0);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
BOOLEAN
|
|
WaitForSpiCycleComplete (
|
|
IN EFI_SPI_PROTOCOL *This,
|
|
IN BOOLEAN ErrorCheck
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Wait execution cycle to complete on the SPI interface. Check both Hardware
|
|
and Software Sequencing status registers
|
|
|
|
Arguments:
|
|
|
|
This - The SPI protocol instance
|
|
UseSoftwareSequence - TRUE if this is a Hardware Sequencing operation
|
|
ErrorCheck - TRUE if the SpiCycle needs to do the error check
|
|
|
|
Returns:
|
|
|
|
TRUE SPI cycle completed on the interface.
|
|
FALSE Time out while waiting the SPI cycle to complete.
|
|
It's not safe to program the next command on the SPI interface.
|
|
|
|
--*/
|
|
{
|
|
UINT64 WaitTicks;
|
|
UINT64 WaitCount;
|
|
UINT16 Data16;
|
|
SPI_INSTANCE *SpiInstance;
|
|
UINTN PchRootComplexBar;
|
|
|
|
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
|
|
PchRootComplexBar = SpiInstance->PchRootComplexBar;
|
|
|
|
//
|
|
// Convert the wait period allowed into to tick count
|
|
//
|
|
WaitCount = WAIT_TIME / WAIT_PERIOD;
|
|
|
|
//
|
|
// Wait for the SPI cycle to complete.
|
|
//
|
|
for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
|
|
Data16 = MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS);
|
|
if ((Data16 & B_QNC_RCRB_SPIS_SCIP) == 0) {
|
|
MmioWrite16 (PchRootComplexBar + R_QNC_RCRB_SPIS, (B_QNC_RCRB_SPIS_BAS | B_QNC_RCRB_SPIS_CDS));
|
|
if ((Data16 & B_QNC_RCRB_SPIS_BAS) && (ErrorCheck == TRUE)) {
|
|
return FALSE;
|
|
} else {
|
|
return TRUE;
|
|
}
|
|
}
|
|
|
|
MicroSecondDelay (WAIT_PERIOD);
|
|
}
|
|
|
|
return FALSE;
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
SpiProtocolInfo (
|
|
IN EFI_SPI_PROTOCOL *This,
|
|
OUT SPI_INIT_INFO **InitInfoPtr
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Return info about SPI host controller, to help callers usage of Execute
|
|
service.
|
|
|
|
If 0xff is returned as an opcode index in init info struct
|
|
then device does not support the operation.
|
|
|
|
Arguments:
|
|
|
|
This Pointer to the EFI_SPI_PROTOCOL instance.
|
|
InitInfoPtr Pointer to init info written to this memory location.
|
|
|
|
Returns:
|
|
|
|
EFI_SUCCESS Information returned.
|
|
EFI_INVALID_PARAMETER Invalid parameter.
|
|
EFI_NOT_READY Required resources not setup.
|
|
Others Unexpected error happened.
|
|
|
|
--*/
|
|
{
|
|
SPI_INSTANCE *SpiInstance;
|
|
|
|
if (This == NULL || InitInfoPtr == NULL) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
|
|
if (SpiInstance->Signature != PCH_SPI_PRIVATE_DATA_SIGNATURE) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
if (!SpiInstance->InitDone) {
|
|
*InitInfoPtr = NULL;
|
|
return EFI_NOT_READY;
|
|
}
|
|
*InitInfoPtr = &SpiInstance->InitInfo;
|
|
return EFI_SUCCESS;
|
|
}
|