mirror of https://github.com/acidanthera/audk.git
80 lines
2.9 KiB
C
80 lines
2.9 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiPei.h>
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#include <Library/ArmLib.h>
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#include <Library/PrePiLib.h>
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#include <Library/PcdLib.h>
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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// SoC registers. L3 interconnects
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#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000
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#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000
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#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
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// SoC registers. L4 interconnects
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#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000
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#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000
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#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
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VOID
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InitCache (
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IN UINT32 MemoryBase,
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IN UINT32 MemoryLength
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)
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{
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UINT32 CacheAttributes;
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ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[5];
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VOID *TranslationTableBase;
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UINTN TranslationTableSize;
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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CacheAttributes = DDR_ATTRIBUTES_CACHED;
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} else {
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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}
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// DDR
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MemoryTable[0].PhysicalBase = MemoryBase;
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MemoryTable[0].VirtualBase = MemoryBase;
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MemoryTable[0].Length = MemoryLength;
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MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
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// SOC Registers. L3 interconnects
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MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
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MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
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MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
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MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;
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// SOC Registers. L4 interconnects
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MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
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MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
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MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
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MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;
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// End of Table
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MemoryTable[3].PhysicalBase = 0;
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MemoryTable[3].VirtualBase = 0;
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MemoryTable[3].Length = 0;
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MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
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BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
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}
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