mirror of https://github.com/acidanthera/audk.git
406 lines
14 KiB
C
406 lines
14 KiB
C
/**
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Copyright (c) 2006 - 2007, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PciCfgInternal.h"
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/**
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@par Ppi Description:
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The EFI_PEI_PCI_CFG2_PPI interfaces are used to abstract
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accesses to PCI controllers behind a PCI root bridge
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controller.
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@param Read PCI read services. See the Read() function description.
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@param Write PCI write services. See the Write() function description.
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@param Modify PCI read-modify-write services. See the Modify() function description.
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@param Segment The PCI bus segment which the specified functions will access.
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**/
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GLOBAL_REMOVE_IF_UNREFERENCED
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EFI_PEI_PCI_CFG2_PPI gPciCfg2Ppi = {
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PciCfg2Read,
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PciCfg2Write,
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PciCfg2Modify
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};
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GLOBAL_REMOVE_IF_UNREFERENCED
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EFI_PEI_PPI_DESCRIPTOR gPciCfg2PpiList = {
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPciCfg2PpiGuid,
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&gPciCfg2Ppi
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};
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/**
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@par Ppi Description:
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The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
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controllers behind a PCI root bridge controller.
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@param Read PCI read services. See the Read() function description.
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@param Write PCI write services. See the Write() function description.
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@param Modify PCI read-modify-write services. See the Modify() function description.
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@param Segment The PCI bus segment which the specified functions will access.
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**/
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GLOBAL_REMOVE_IF_UNREFERENCED
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EFI_PEI_PCI_CFG_PPI gPciCfgPpi = {
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PciCfgRead,
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PciCfgWrite,
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PciCfgModify
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};
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GLOBAL_REMOVE_IF_UNREFERENCED
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EFI_PEI_PPI_DESCRIPTOR gPciCfgPpiList = {
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPciCfgPpiInServiceTableGuid,
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&gPciCfgPpi
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};
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/**
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Convert EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS to PCI_LIB_ADDRESS.
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@param Address PCI address with
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EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS format.
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@return The PCI address with PCI_LIB_ADDRESS format.
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**/
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UINTN
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PciCfgAddressConvert (
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EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *Address
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)
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{
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if (Address->ExtendedRegister == 0) {
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return PCI_LIB_ADDRESS (Address->Bus, Address->Device, Address->Function, Address->Register);
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}
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return PCI_LIB_ADDRESS (Address->Bus, Address->Device, Address->Function, Address->ExtendedRegister);
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}
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/**
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Reads from a given location in the PCI configuration space.
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@param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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@param This Pointer to local data for the interface.
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@param Width The width of the access. Enumerated in bytes.
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See EFI_PEI_PCI_CFG_PPI_WIDTH above.
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@param Address The physical address of the access. The format of
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the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
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@param Buffer A pointer to the buffer of data..
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_DEVICE_ERROR There was a problem with the transaction.
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@retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this
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time.
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**/
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EFI_STATUS
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EFIAPI
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PciCfg2Read (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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IN UINT64 Address,
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IN OUT VOID *Buffer
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)
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{
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UINTN PciLibAddress;
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PciLibAddress = PciCfgAddressConvert ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &Address);
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if (Width == EfiPeiPciCfgWidthUint8) {
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*((UINT8 *) Buffer) = PciRead8 (PciLibAddress);
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} else if (Width == EfiPeiPciCfgWidthUint16) {
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if ((PciLibAddress & 0x01) == 0) {
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//
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// Aligned Pci address access
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//
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WriteUnaligned16 (((UINT16 *) Buffer), PciRead16 (PciLibAddress));
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} else {
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//
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// Unaligned Pci address access, break up the request into byte by byte.
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//
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*((UINT8 *) Buffer) = PciRead8 (PciLibAddress);
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*((UINT8 *) Buffer + 1) = PciRead8 (PciLibAddress + 1);
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}
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} else if (Width == EfiPeiPciCfgWidthUint32) {
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if ((PciLibAddress & 0x03) == 0) {
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//
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// Aligned Pci address access
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//
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WriteUnaligned32 (((UINT32 *) Buffer), PciRead32 (PciLibAddress));
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} else if ((PciLibAddress & 0x01) == 0) {
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//
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// Unaligned Pci address access, break up the request into word by word.
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//
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WriteUnaligned16 (((UINT16 *) Buffer), PciRead16 (PciLibAddress));
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WriteUnaligned16 (((UINT16 *) Buffer + 1), PciRead16 (PciLibAddress + 2));
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} else {
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//
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// Unaligned Pci address access, break up the request into byte by byte.
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//
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*((UINT8 *) Buffer) = PciRead8 (PciLibAddress);
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*((UINT8 *) Buffer + 1) = PciRead8 (PciLibAddress + 1);
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*((UINT8 *) Buffer + 2) = PciRead8 (PciLibAddress + 2);
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*((UINT8 *) Buffer + 3) = PciRead8 (PciLibAddress + 3);
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}
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} else {
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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/**
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Write to a given location in the PCI configuration space.
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@param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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@param This Pointer to local data for the interface.
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@param Width The width of the access. Enumerated in bytes.
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See EFI_PEI_PCI_CFG_PPI_WIDTH above.
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@param Address The physical address of the access. The format of
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the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
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@param Buffer A pointer to the buffer of data..
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_DEVICE_ERROR There was a problem with the transaction.
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@retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this
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time.
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**/
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EFI_STATUS
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EFIAPI
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PciCfg2Write (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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IN UINT64 Address,
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IN OUT VOID *Buffer
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)
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{
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UINTN PciLibAddress;
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PciLibAddress = PciCfgAddressConvert ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &Address);
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if (Width == EfiPeiPciCfgWidthUint8) {
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PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));
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} else if (Width == EfiPeiPciCfgWidthUint16) {
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if ((PciLibAddress & 0x01) == 0) {
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//
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// Aligned Pci address access
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//
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PciWrite16 (PciLibAddress, ReadUnaligned16 ((UINT16 *) Buffer));
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} else {
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//
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// Unaligned Pci address access, break up the request into byte by byte.
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//
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PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));
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PciWrite8 (PciLibAddress + 1, *((UINT8 *) Buffer + 1));
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}
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} else if (Width == EfiPeiPciCfgWidthUint32) {
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if ((PciLibAddress & 0x03) == 0) {
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//
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// Aligned Pci address access
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//
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PciWrite32 (PciLibAddress, ReadUnaligned32 ((UINT32 *) Buffer));
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} else if ((PciLibAddress & 0x01) == 0) {
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//
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// Unaligned Pci address access, break up the request into word by word.
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//
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PciWrite16 (PciLibAddress, ReadUnaligned16 ((UINT16 *) Buffer));
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PciWrite16 (PciLibAddress + 2, ReadUnaligned16 ((UINT16 *) Buffer + 1));
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} else {
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//
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// Unaligned Pci address access, break up the request into byte by byte.
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//
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PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));
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PciWrite8 (PciLibAddress + 1, *((UINT8 *) Buffer + 1));
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PciWrite8 (PciLibAddress + 2, *((UINT8 *) Buffer + 2));
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PciWrite8 (PciLibAddress + 3, *((UINT8 *) Buffer + 3));
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}
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} else {
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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/**
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PCI read-modify-write operation.
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@param PeiServices An indirect pointer to the PEI Services Table
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published by the PEI Foundation.
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@param This Pointer to local data for the interface.
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@param Width The width of the access. Enumerated in bytes. Type
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EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
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@param Address The physical address of the access.
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@param SetBits Points to value to bitwise-OR with the read configuration value.
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The size of the value is determined by Width.
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@param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.
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The size of the value is determined by Width.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_DEVICE_ERROR There was a problem with the transaction.
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@retval EFI_DEVICE_NOT_READY The device is not capable of supporting
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the operation at this time.
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**/
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EFI_STATUS
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EFIAPI
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PciCfg2Modify (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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IN UINT64 Address,
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IN VOID *SetBits,
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IN VOID *ClearBits
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)
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{
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UINTN PciLibAddress;
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UINT16 ClearValue16;
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UINT16 SetValue16;
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UINT32 ClearValue32;
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UINT32 SetValue32;
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PciLibAddress = PciCfgAddressConvert ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &Address);
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if (Width == EfiPeiPciCfgWidthUint8) {
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PciAndThenOr8 (PciLibAddress, (UINT8) (~(*(UINT8 *) ClearBits)), *((UINT8 *) SetBits));
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} else if (Width == EfiPeiPciCfgWidthUint16) {
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if ((PciLibAddress & 0x01) == 0) {
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//
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// Aligned Pci address access
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//
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ClearValue16 = (UINT16) (~ReadUnaligned16 ((UINT16 *) ClearBits));
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SetValue16 = ReadUnaligned16 ((UINT16 *) SetBits);
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PciAndThenOr16 (PciLibAddress, ClearValue16, SetValue16);
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} else {
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//
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// Unaligned Pci address access, break up the request into byte by byte.
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//
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PciAndThenOr8 (PciLibAddress, (UINT8) (~(*(UINT8 *) ClearBits)), *((UINT8 *) SetBits));
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PciAndThenOr8 (PciLibAddress + 1, (UINT8) (~(*((UINT8 *) ClearBits + 1))), *((UINT8 *) SetBits + 1));
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}
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} else if (Width == EfiPeiPciCfgWidthUint32) {
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if ((PciLibAddress & 0x03) == 0) {
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//
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// Aligned Pci address access
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//
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ClearValue32 = (UINT32) (~ReadUnaligned32 ((UINT32 *) ClearBits));
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SetValue32 = ReadUnaligned32 ((UINT32 *) SetBits);
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PciAndThenOr32 (PciLibAddress, ClearValue32, SetValue32);
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} else if ((PciLibAddress & 0x01) == 0) {
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//
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// Unaligned Pci address access, break up the request into word by word.
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//
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ClearValue16 = (UINT16) (~ReadUnaligned16 ((UINT16 *) ClearBits));
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SetValue16 = ReadUnaligned16 ((UINT16 *) SetBits);
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PciAndThenOr16 (PciLibAddress, ClearValue16, SetValue16);
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ClearValue16 = (UINT16) (~ReadUnaligned16 ((UINT16 *) ClearBits + 1));
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SetValue16 = ReadUnaligned16 ((UINT16 *) SetBits + 1);
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PciAndThenOr16 (PciLibAddress + 2, ClearValue16, SetValue16);
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} else {
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//
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// Unaligned Pci address access, break up the request into byte by byte.
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//
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PciAndThenOr8 (PciLibAddress, (UINT8) (~(*(UINT8 *) ClearBits)), *((UINT8 *) SetBits));
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PciAndThenOr8 (PciLibAddress + 1, (UINT8) (~(*((UINT8 *) ClearBits + 1))), *((UINT8 *) SetBits + 1));
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PciAndThenOr8 (PciLibAddress + 2, (UINT8) (~(*((UINT8 *) ClearBits + 2))), *((UINT8 *) SetBits + 2));
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PciAndThenOr8 (PciLibAddress + 3, (UINT8) (~(*((UINT8 *) ClearBits + 3))), *((UINT8 *) SetBits + 3));
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}
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} else {
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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/**
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Module's entry function.
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This routine will install EFI_PEI_PCI_CFG2_PPI or EFI_PEI_PCI_CFG_PPI
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according to PeiServices's version.
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@param FileHandle Handle of the file being invoked.
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@param PeiServices Describes the list of possible PEI Services.
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@return Whether success to install service
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**/
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EFI_STATUS
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EFIAPI
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PeimInitializePciCfg (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_STATUS Status;
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Status = EFI_SUCCESS;
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if ((**PeiServices).Hdr.Revision < PEI_SERVICES_REVISION) {
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//
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// BugBug: Curently, the FrameworkPkg does not define
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// FRAMEWORK_PEI_SERVICES. So, In order to install
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// the PeiServices.PciCfg(), we casttype
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// EFI_PEI_PCI_CFG_PPI to EFI_PEI_PCI_CFG2_PPI.
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// After defining the FRAMEWORK_PEI_SERVICES. this should
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// be updated as:
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//
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// FrameworkPeiServices = (FRAMEWORK_PEI_SERVICES **) PeiServices;
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// (**FrameworkPeiServices).PciCfg = &mPciCfgPpi;
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//
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(**(EFI_PEI_SERVICES**)PeiServices).PciCfg = (EFI_PEI_PCI_CFG2_PPI *) &gPciCfgPpi;
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} else {
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(**(EFI_PEI_SERVICES**)PeiServices).PciCfg = &gPciCfg2Ppi;
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}
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if (!FeaturePcdGet (PcdPciCfgDisable)) {
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Status = (**PeiServices).InstallPpi (PeiServices, &gPciCfgPpiList);
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}
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if (!FeaturePcdGet (PcdPciCfg2Disable)) {
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Status = (**PeiServices).InstallPpi (PeiServices, &gPciCfg2PpiList);
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}
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return Status;
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}
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