mirror of https://github.com/acidanthera/audk.git
235 lines
7.6 KiB
C
235 lines
7.6 KiB
C
/** @file
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <PiPei.h>
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#include <Library/DebugAgentLib.h>
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#include <Library/PrePiLib.h>
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#include <Library/PrintLib.h>
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#include <Library/PeCoffGetEntryPointLib.h>
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#include <Library/PrePiHobListPointerLib.h>
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#include <Library/TimerLib.h>
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#include <Library/PerformanceLib.h>
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#include <Ppi/GuidedSectionExtraction.h>
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#include <Ppi/ArmMpCoreInfo.h>
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#include <Guid/LzmaDecompress.h>
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#include "PrePi.h"
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#include "LzmaDecompress.h"
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#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \
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((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))
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UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +
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FixedPcdGet64(PcdSystemMemorySize) - 1;
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EFI_STATUS
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EFIAPI
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ExtractGuidedSectionLibConstructor (
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VOID
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);
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EFI_STATUS
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EFIAPI
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LzmaDecompressLibConstructor (
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VOID
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);
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EFI_STATUS
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GetPlatformPpi (
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IN EFI_GUID *PpiGuid,
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OUT VOID **Ppi
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)
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{
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UINTN PpiListSize;
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UINTN PpiListCount;
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EFI_PEI_PPI_DESCRIPTOR *PpiList;
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UINTN Index;
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PpiListSize = 0;
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ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
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PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
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for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
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if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
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*Ppi = PpiList->Ppi;
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return EFI_SUCCESS;
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}
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}
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return EFI_NOT_FOUND;
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}
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VOID
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PrePiMain (
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase,
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IN UINT64 StartTimeStamp
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)
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{
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EFI_HOB_HANDOFF_INFO_TABLE* HobList;
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ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi;
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UINTN ArmCoreCount;
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ARM_CORE_INFO* ArmCoreInfoTable;
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EFI_STATUS Status;
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CHAR8 Buffer[100];
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UINTN CharCount;
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UINTN StacksSize;
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// If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
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ASSERT (IS_XIP() ||
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((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
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((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));
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// Initialize the architecture specific bits
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ArchInitialize ();
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// Initialize the Serial Port
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SerialPortInitialize ();
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
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(CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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// Initialize the Debug Agent for Source Level Debugging
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InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
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SaveAndSetDebugTimerInterrupt (TRUE);
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// Declare the PI/UEFI memory region
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HobList = HobConstructor (
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(VOID*)UefiMemoryBase,
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FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
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(VOID*)UefiMemoryBase,
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(VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks
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);
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PrePeiSetHobList (HobList);
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// Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
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Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
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ASSERT_EFI_ERROR (Status);
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// Create the Stacks HOB (reserve the memory for all stacks)
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if (ArmIsMpCore ()) {
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StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
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((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
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} else {
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StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
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}
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BuildStackHob (StacksBase, StacksSize);
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//TODO: Call CpuPei as a library
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BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));
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if (ArmIsMpCore ()) {
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// Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
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Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
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// On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
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ASSERT_EFI_ERROR (Status);
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// Build the MP Core Info Table
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ArmCoreCount = 0;
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Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
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if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
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// Build MPCore Info HOB
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BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
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}
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}
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// Set the Boot Mode
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SetBootMode (ArmPlatformGetBootMode ());
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// Initialize Platform HOBs (CpuHob and FvHob)
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Status = PlatformPeim ();
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ASSERT_EFI_ERROR (Status);
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// Now, the HOB List has been initialized, we can register performance information
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PERF_START (NULL, "PEI", NULL, StartTimeStamp);
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// SEC phase needs to run library constructors by hand.
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ExtractGuidedSectionLibConstructor ();
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LzmaDecompressLibConstructor ();
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// Build HOBs to pass up our version of stuff the DXE Core needs to save space
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BuildPeCoffLoaderHob ();
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BuildExtractSectionHob (
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&gLzmaCustomDecompressGuid,
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LzmaGuidedSectionGetInfo,
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LzmaGuidedSectionExtraction
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);
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// Assume the FV that contains the SEC (our code) also contains a compressed FV.
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Status = DecompressFirstFv ();
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ASSERT_EFI_ERROR (Status);
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// Load the DXE Core and transfer control to it
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Status = LoadDxeCoreFromFv (NULL, 0);
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ASSERT_EFI_ERROR (Status);
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}
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VOID
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CEntryPoint (
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IN UINTN MpId,
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase
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)
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{
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UINT64 StartTimeStamp;
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// Initialize the platform specific controllers
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ArmPlatformInitialize (MpId);
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if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
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// Initialize the Timer Library to setup the Timer HW controller
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TimerConstructor ();
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// We cannot call yet the PerformanceLib because the HOB List has not been initialized
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StartTimeStamp = GetPerformanceCounter ();
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} else {
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StartTimeStamp = 0;
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}
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// Data Cache enabled on Primary core when MMU is enabled.
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ArmDisableDataCache ();
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// Invalidate Data cache
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ArmInvalidateDataCache ();
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// Invalidate instruction cache
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ArmInvalidateInstructionCache ();
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// Enable Instruction Caches on all cores.
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ArmEnableInstructionCache ();
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// Define the Global Variable region when we are not running in XIP
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if (!IS_XIP()) {
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if (ArmPlatformIsPrimaryCore (MpId)) {
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if (ArmIsMpCore()) {
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// Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
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ArmCallSEV ();
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}
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} else {
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// Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
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ArmCallWFE ();
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}
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}
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// If not primary Jump to Secondary Main
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if (ArmPlatformIsPrimaryCore (MpId)) {
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// Goto primary Main.
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PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
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} else {
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SecondaryMain (MpId);
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}
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// DXE Core should always load and never return
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ASSERT (FALSE);
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}
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