mirror of https://github.com/acidanthera/audk.git
506 lines
18 KiB
C
506 lines
18 KiB
C
/** @file
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Code for Processor S3 restoration
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Copyright (c) 2006 - 2024, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PiSmmCpuDxeSmm.h"
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#include <PiPei.h>
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//
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// Flags used when program the register.
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//
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typedef struct {
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volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
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volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program
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// core level semaphore.
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volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program
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// package level semaphore.
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} PROGRAM_CPU_REGISTER_FLAGS;
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#define LEGACY_REGION_SIZE (2 * 0x1000)
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#define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
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ACPI_CPU_DATA mAcpiCpuData;
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BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
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//
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// S3 boot flag
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//
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BOOLEAN mSmmS3Flag = FALSE;
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//
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// Pointer to structure used during S3 Resume
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//
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SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
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BOOLEAN mAcpiS3Enable = TRUE;
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/**
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Restore SMM Configuration in S3 boot path.
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**/
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VOID
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RestoreSmmConfigurationInS3 (
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VOID
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)
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{
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if (!mAcpiS3Enable) {
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return;
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}
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//
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// Restore SMM Configuration in S3 boot path.
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//
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if (mRestoreSmmConfigurationInS3) {
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//
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// Need make sure gSmst is correct because below function may use them.
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//
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gSmst->SmmStartupThisAp = gSmmCpuPrivate->SmmCoreEntryContext.SmmStartupThisAp;
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gSmst->CurrentlyExecutingCpu = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
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gSmst->NumberOfCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
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gSmst->CpuSaveStateSize = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveStateSize;
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gSmst->CpuSaveState = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveState;
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//
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// Configure SMM Code Access Check feature if available.
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//
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ConfigSmmCodeAccessCheck ();
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SmmCpuFeaturesCompleteSmmReadyToLock ();
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mRestoreSmmConfigurationInS3 = FALSE;
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}
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}
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/**
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Perform SMM initialization for all processors in the S3 boot path.
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For a native platform, MP initialization in the S3 boot path is also performed in this function.
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**/
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VOID
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EFIAPI
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SmmRestoreCpu (
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VOID
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)
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{
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SMM_S3_RESUME_STATE *SmmS3ResumeState;
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IA32_DESCRIPTOR Ia32Idtr;
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IA32_DESCRIPTOR X64Idtr;
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IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n"));
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mSmmS3Flag = TRUE;
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//
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// See if there is enough context to resume PEI Phase
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//
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if (mSmmS3ResumeState == NULL) {
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DEBUG ((DEBUG_ERROR, "No context to return to PEI Phase\n"));
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CpuDeadLoop ();
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}
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SmmS3ResumeState = mSmmS3ResumeState;
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ASSERT (SmmS3ResumeState != NULL);
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//
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// Setup 64bit IDT in 64bit SMM env when called from 32bit PEI.
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// Note: 64bit PEI and 32bit DXE is not a supported combination.
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//
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if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) && (FeaturePcdGet (PcdDxeIplSwitchToLongMode) == TRUE)) {
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//
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// Save the IA32 IDT Descriptor
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//
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AsmReadIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
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//
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// Setup X64 IDT table
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//
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ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
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X64Idtr.Base = (UINTN)IdtEntryTable;
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X64Idtr.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
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AsmWriteIdtr ((IA32_DESCRIPTOR *)&X64Idtr);
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//
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// Setup the default exception handler
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//
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Status = InitializeCpuExceptionHandlers (NULL);
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ASSERT_EFI_ERROR (Status);
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//
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// Initialize Debug Agent to support source level debug
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//
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if (mSmmDebugAgentSupport) {
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InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
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}
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}
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//
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// Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init.
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//
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ExecuteFirstSmiInit ();
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//
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// Set a flag to restore SMM configuration in S3 path.
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//
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mRestoreSmmConfigurationInS3 = TRUE;
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DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
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DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
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DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
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DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
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DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
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//
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// If SMM is in 32-bit mode or PcdDxeIplSwitchToLongMode is FALSE, then use SwitchStack() to resume PEI Phase.
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// Note: 64bit PEI and 32bit DXE is not a supported combination.
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//
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if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode) == FALSE)) {
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DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
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SwitchStack (
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(SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
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(VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,
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(VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,
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(VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer
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);
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}
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//
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// If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
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//
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if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
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DEBUG ((DEBUG_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
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//
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// Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
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//
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SaveAndSetDebugTimerInterrupt (FALSE);
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//
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// Restore IA32 IDT table
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//
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AsmWriteIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
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AsmDisablePaging64 (
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SmmS3ResumeState->ReturnCs,
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(UINT32)SmmS3ResumeState->ReturnEntryPoint,
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(UINT32)SmmS3ResumeState->ReturnContext1,
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(UINT32)SmmS3ResumeState->ReturnContext2,
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(UINT32)SmmS3ResumeState->ReturnStackPointer
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);
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}
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//
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// Can not resume PEI Phase
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//
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DEBUG ((DEBUG_ERROR, "No context to return to PEI Phase\n"));
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CpuDeadLoop ();
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}
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/**
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Initialize SMM S3 resume state structure used during S3 Resume.
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@param[in] Cr3 The base address of the page tables to use in SMM.
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**/
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VOID
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InitSmmS3ResumeState (
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IN UINT32 Cr3
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)
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{
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VOID *GuidHob;
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EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
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SMM_S3_RESUME_STATE *SmmS3ResumeState;
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if (!mAcpiS3Enable) {
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return;
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}
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GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
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if (GuidHob == NULL) {
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DEBUG ((
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DEBUG_ERROR,
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"ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",
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__func__,
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&gEfiAcpiVariableGuid
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));
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CpuDeadLoop ();
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} else {
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SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);
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DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
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DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
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SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
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ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));
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mSmmS3ResumeState = SmmS3ResumeState;
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SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;
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SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;
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SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;
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SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));
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if (SmmS3ResumeState->SmmS3StackBase == 0) {
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SmmS3ResumeState->SmmS3StackSize = 0;
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}
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SmmS3ResumeState->SmmS3Cr0 = (UINT32)AsmReadCr0 ();
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SmmS3ResumeState->SmmS3Cr3 = Cr3;
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SmmS3ResumeState->SmmS3Cr4 = (UINT32)AsmReadCr4 ();
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if (sizeof (UINTN) == sizeof (UINT64)) {
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SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
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}
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if (sizeof (UINTN) == sizeof (UINT32)) {
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SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
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}
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//
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// Patch SmmS3ResumeState->SmmS3Cr3
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//
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InitSmmS3Cr3 ();
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}
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}
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/**
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Copy register table from non-SMRAM into SMRAM.
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@param[in] DestinationRegisterTableList Points to destination register table.
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@param[in] SourceRegisterTableList Points to source register table.
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@param[in] NumberOfCpus Number of CPUs.
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**/
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VOID
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CopyRegisterTable (
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IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
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IN CPU_REGISTER_TABLE *SourceRegisterTableList,
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IN UINT32 NumberOfCpus
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)
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{
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UINTN Index;
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CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
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CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
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for (Index = 0; Index < NumberOfCpus; Index++) {
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if (DestinationRegisterTableList[Index].TableLength != 0) {
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DestinationRegisterTableList[Index].AllocatedSize = DestinationRegisterTableList[Index].TableLength * sizeof (CPU_REGISTER_TABLE_ENTRY);
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RegisterTableEntry = AllocateCopyPool (
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DestinationRegisterTableList[Index].AllocatedSize,
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(VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
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);
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ASSERT (RegisterTableEntry != NULL);
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DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
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}
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}
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}
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/**
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Check whether the register table is empty or not.
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@param[in] RegisterTable Point to the register table.
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@param[in] NumberOfCpus Number of CPUs.
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@retval TRUE The register table is empty.
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@retval FALSE The register table is not empty.
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**/
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BOOLEAN
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IsRegisterTableEmpty (
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IN CPU_REGISTER_TABLE *RegisterTable,
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IN UINT32 NumberOfCpus
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)
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{
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UINTN Index;
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if (RegisterTable != NULL) {
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for (Index = 0; Index < NumberOfCpus; Index++) {
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if (RegisterTable[Index].TableLength != 0) {
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return FALSE;
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}
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}
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}
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return TRUE;
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}
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/**
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Copy the data used to initialize processor register into SMRAM.
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@param[in,out] CpuFeatureInitDataDst Pointer to the destination CPU_FEATURE_INIT_DATA structure.
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@param[in] CpuFeatureInitDataSrc Pointer to the source CPU_FEATURE_INIT_DATA structure.
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**/
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VOID
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CopyCpuFeatureInitDatatoSmram (
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IN OUT CPU_FEATURE_INIT_DATA *CpuFeatureInitDataDst,
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IN CPU_FEATURE_INIT_DATA *CpuFeatureInitDataSrc
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)
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{
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CPU_STATUS_INFORMATION *CpuStatus;
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if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus)) {
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CpuFeatureInitDataDst->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
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ASSERT (CpuFeatureInitDataDst->PreSmmInitRegisterTable != 0);
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CopyRegisterTable (
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(CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataDst->PreSmmInitRegisterTable,
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(CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegisterTable,
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mAcpiCpuData.NumberOfCpus
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);
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}
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if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->RegisterTable, mAcpiCpuData.NumberOfCpus)) {
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CpuFeatureInitDataDst->RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
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ASSERT (CpuFeatureInitDataDst->RegisterTable != 0);
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CopyRegisterTable (
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(CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataDst->RegisterTable,
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(CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->RegisterTable,
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mAcpiCpuData.NumberOfCpus
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);
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}
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CpuStatus = &CpuFeatureInitDataDst->CpuStatus;
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CopyMem (CpuStatus, &CpuFeatureInitDataSrc->CpuStatus, sizeof (CPU_STATUS_INFORMATION));
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if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage != 0) {
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CpuStatus->ThreadCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
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sizeof (UINT32) * CpuStatus->PackageCount,
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(UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage
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);
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ASSERT (CpuStatus->ThreadCountPerPackage != 0);
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}
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if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore != 0) {
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CpuStatus->ThreadCountPerCore = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
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sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount),
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(UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore
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);
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ASSERT (CpuStatus->ThreadCountPerCore != 0);
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}
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if (CpuFeatureInitDataSrc->ApLocation != 0) {
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CpuFeatureInitDataDst->ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
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mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),
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(EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation
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);
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ASSERT (CpuFeatureInitDataDst->ApLocation != 0);
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}
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}
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/**
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Get ACPI CPU data.
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**/
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VOID
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GetAcpiCpuData (
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VOID
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)
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{
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ACPI_CPU_DATA *AcpiCpuData;
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IA32_DESCRIPTOR *Gdtr;
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IA32_DESCRIPTOR *Idtr;
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VOID *GdtForAp;
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VOID *IdtForAp;
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VOID *MachineCheckHandlerForAp;
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CPU_STATUS_INFORMATION *CpuStatus;
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if (!mAcpiS3Enable) {
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return;
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}
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//
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// Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
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//
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mAcpiCpuData.NumberOfCpus = 0;
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//
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// If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
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//
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AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
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if (AcpiCpuData == 0) {
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return;
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}
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//
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// For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
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//
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CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));
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mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));
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ASSERT (mAcpiCpuData.MtrrTable != 0);
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CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));
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mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
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ASSERT (mAcpiCpuData.GdtrProfile != 0);
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CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));
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mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
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ASSERT (mAcpiCpuData.IdtrProfile != 0);
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CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));
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//
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// Copy AP's GDT, IDT and Machine Check handler into SMRAM.
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//
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Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;
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Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;
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GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
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ASSERT (GdtForAp != NULL);
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IdtForAp = (VOID *)((UINTN)GdtForAp + (Gdtr->Limit + 1));
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MachineCheckHandlerForAp = (VOID *)((UINTN)IdtForAp + (Idtr->Limit + 1));
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CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
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CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
|
|
CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);
|
|
|
|
Gdtr->Base = (UINTN)GdtForAp;
|
|
Idtr->Base = (UINTN)IdtForAp;
|
|
mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;
|
|
|
|
ZeroMem (&mAcpiCpuData.CpuFeatureInitData, sizeof (CPU_FEATURE_INIT_DATA));
|
|
|
|
if (!PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) {
|
|
//
|
|
// If the CPU features will not be initialized by CpuFeaturesPei module during
|
|
// next ACPI S3 resume, copy the CPU features initialization data into SMRAM,
|
|
// which will be consumed in SmmRestoreCpu during next S3 resume.
|
|
//
|
|
CopyCpuFeatureInitDatatoSmram (&mAcpiCpuData.CpuFeatureInitData, &AcpiCpuData->CpuFeatureInitData);
|
|
|
|
CpuStatus = &mAcpiCpuData.CpuFeatureInitData.CpuStatus;
|
|
|
|
mCpuFlags.CoreSemaphoreCount = AllocateZeroPool (
|
|
sizeof (UINT32) * CpuStatus->PackageCount *
|
|
CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
|
|
);
|
|
ASSERT (mCpuFlags.CoreSemaphoreCount != NULL);
|
|
|
|
mCpuFlags.PackageSemaphoreCount = AllocateZeroPool (
|
|
sizeof (UINT32) * CpuStatus->PackageCount *
|
|
CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
|
|
);
|
|
ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
|
|
|
|
InitializeSpinLock ((SPIN_LOCK *)&mCpuFlags.MemoryMappedLock);
|
|
}
|
|
}
|
|
|
|
/**
|
|
Get ACPI S3 enable flag.
|
|
|
|
**/
|
|
VOID
|
|
GetAcpiS3EnableFlag (
|
|
VOID
|
|
)
|
|
{
|
|
mAcpiS3Enable = PcdGetBool (PcdAcpiS3Enable);
|
|
}
|