mirror of https://github.com/acidanthera/audk.git
374 lines
14 KiB
C
374 lines
14 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Drivers/PL341Dmc.h>
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//
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// DMC Configuration Register Map
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//
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#define DMC_STATUS_REG 0x00
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#define DMC_COMMAND_REG 0x04
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#define DMC_DIRECT_CMD_REG 0x08
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#define DMC_MEMORY_CONFIG_REG 0x0C
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#define DMC_REFRESH_PRD_REG 0x10
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#define DMC_CAS_LATENCY_REG 0x14
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#define DMC_WRITE_LATENCY_REG 0x18
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#define DMC_T_MRD_REG 0x1C
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#define DMC_T_RAS_REG 0x20
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#define DMC_T_RC_REG 0x24
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#define DMC_T_RCD_REG 0x28
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#define DMC_T_RFC_REG 0x2C
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#define DMC_T_RP_REG 0x30
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#define DMC_T_RRD_REG 0x34
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#define DMC_T_WR_REG 0x38
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#define DMC_T_WTR_REG 0x3C
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#define DMC_T_XP_REG 0x40
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#define DMC_T_XSR_REG 0x44
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#define DMC_T_ESR_REG 0x48
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#define DMC_MEMORY_CFG2_REG 0x4C
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#define DMC_MEMORY_CFG3_REG 0x50
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#define DMC_T_FAW_REG 0x54
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// Returns the state of the memory controller:
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#define DMC_STATUS_CONFIG 0x0
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#define DMC_STATUS_READY 0x1
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#define DMC_STATUS_PAUSED 0x2
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#define DMC_STATUS_LOWPOWER 0x3
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// Changes the state of the memory controller:
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#define DMC_COMMAND_GO 0x0
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#define DMC_COMMAND_SLEEP 0x1
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#define DMC_COMMAND_WAKEUP 0x2
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#define DMC_COMMAND_PAUSE 0x3
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#define DMC_COMMAND_CONFIGURE 0x4
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#define DMC_COMMAND_ACTIVEPAUSE 0x7
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// Determines the command required
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#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
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#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
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#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
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#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
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//
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// AXI ID configuration register map
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//
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#define DMC_ID_0_CFG_REG 0x100
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#define DMC_ID_1_CFG_REG 0x104
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#define DMC_ID_2_CFG_REG 0x108
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#define DMC_ID_3_CFG_REG 0x10C
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#define DMC_ID_4_CFG_REG 0x110
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#define DMC_ID_5_CFG_REG 0x114
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#define DMC_ID_6_CFG_REG 0x118
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#define DMC_ID_7_CFG_REG 0x11C
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#define DMC_ID_8_CFG_REG 0x120
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#define DMC_ID_9_CFG_REG 0x124
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#define DMC_ID_10_CFG_REG 0x128
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#define DMC_ID_11_CFG_REG 0x12C
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#define DMC_ID_12_CFG_REG 0x130
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#define DMC_ID_13_CFG_REG 0x134
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#define DMC_ID_14_CFG_REG 0x138
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#define DMC_ID_15_CFG_REG 0x13C
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// Set the QoS
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#define DMC_ID_CFG_QOS_DISABLE 0
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#define DMC_ID_CFG_QOS_ENABLE 1
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#define DMC_ID_CFG_QOS_MIN 2
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//
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// Chip configuration register map
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//
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#define DMC_CHIP_0_CFG_REG 0x200
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#define DMC_CHIP_1_CFG_REG 0x204
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#define DMC_CHIP_2_CFG_REG 0x208
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#define DMC_CHIP_3_CFG_REG 0x20C
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//
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// User Defined Pins
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//
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#define DMC_USER_STATUS_REG 0x300
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#define DMC_USER_0_CFG_REG 0x304
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#define DMC_USER_1_CFG_REG 0x308
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#define DMC_FEATURE_CRTL_REG 0x30C
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#define DMC_USER_2_CFG_REG 0x310
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//
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// PHY Register Settings
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//
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#define TC_UIOLHNC_MASK 0x000003C0
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#define TC_UIOLHNC_SHIFT 0x6
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#define TC_UIOLHPC_MASK 0x0000003F
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#define TC_UIOLHPC_SHIFT 0x2
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#define TC_UIOHOCT_MASK 0x2
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#define TC_UIOHOCT_SHIFT 0x1
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#define TC_UIOHSTOP_SHIFT 0x0
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#define TC_UIOLHXC_VALUE 0x4
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//
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// Extended Mode Register settings
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//
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#define DDR_EMR_OCD_MASK 0x0000380
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#define DDR_EMR_OCD_SHIFT 0x7
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#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
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#define DDR_EMR_RTT_SHIFT 0x2
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#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
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#define DDR_EMR_ODS_SHIFT 0x0001
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// Termination Values:
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#define DDR_EMR_RTT_50 0x00000044 // DDR2 50 Ohm termination
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#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
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#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
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// Output Drive Strength Values:
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#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
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#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
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// OCD values
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#define DDR_EMR_OCD_DEFAULT 0x7
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#define DDR_EMR_OCD_NS 0x0
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#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
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#define DmcWriteReg(reg,val) MmioWrite32(DmcBase + reg, val)
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#define DmcReadReg(reg) MmioRead32(DmcBase + reg)
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// Initialize PL341 Dynamic Memory Controller
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VOID PL341DmcInit(struct pl341_dmc_config *config) {
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UINTN DmcBase = config->base;
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UINT32 i, chip, val32;
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// Set config mode
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DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);
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//
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// Setup the QoS AXI ID bits
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//
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if (config->has_qos) {
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// CLCD AXIID = 000
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DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);
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// Default disable QoS
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DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
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}
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//
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// Initialise memory controlller
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//
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DmcWriteReg(DMC_REFRESH_PRD_REG, config->refresh_prd);
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DmcWriteReg(DMC_CAS_LATENCY_REG, config->cas_latency);
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DmcWriteReg(DMC_WRITE_LATENCY_REG, config->write_latency);
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DmcWriteReg(DMC_T_MRD_REG, config->t_mrd);
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DmcWriteReg(DMC_T_RAS_REG, config->t_ras);
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DmcWriteReg(DMC_T_RC_REG, config->t_rc);
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DmcWriteReg(DMC_T_RCD_REG, config->t_rcd);
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DmcWriteReg(DMC_T_RFC_REG, config->t_rfc);
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DmcWriteReg(DMC_T_RP_REG, config->t_rp);
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DmcWriteReg(DMC_T_RRD_REG, config->t_rrd);
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DmcWriteReg(DMC_T_WR_REG, config->t_wr);
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DmcWriteReg(DMC_T_WTR_REG, config->t_wtr);
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DmcWriteReg(DMC_T_XP_REG, config->t_xp);
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DmcWriteReg(DMC_T_XSR_REG, config->t_xsr);
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DmcWriteReg(DMC_T_ESR_REG, config->t_esr);
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DmcWriteReg(DMC_T_FAW_REG, config->t_faw);
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// =======================================================================
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// Initialise PL341 Mem Config Registers
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// =======================================================================
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// |======================================
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// | Set PL341 Memory Config
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// |======================================
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DmcWriteReg(DMC_MEMORY_CONFIG_REG, config->memory_cfg);
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// |======================================
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// | Set PL341 Memory Config 2
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// |======================================
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DmcWriteReg(DMC_MEMORY_CFG2_REG, config->memory_cfg2);
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// |======================================
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// | Set PL341 Chip Select <n>
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// |======================================
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DmcWriteReg(DMC_CHIP_0_CFG_REG, config->chip_cfg0);
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DmcWriteReg(DMC_CHIP_1_CFG_REG, config->chip_cfg1);
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DmcWriteReg(DMC_CHIP_2_CFG_REG, config->chip_cfg2);
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DmcWriteReg(DMC_CHIP_3_CFG_REG, config->chip_cfg3);
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// |======================================
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// | Set PL341 Memory Config 3
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// |======================================
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DmcWriteReg(DMC_MEMORY_CFG3_REG, config->memory_cfg3);
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// |========================================================
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// |Set Test Chip PHY Registers via PL341 User Config Reg
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// |Note that user_cfgX registers are Write Only
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// |
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// |DLL Freq set = 250MHz - 266MHz
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// |========================================================
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DmcWriteReg(DMC_USER_0_CFG_REG, 0x7C924924);
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// user_config2
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// ------------
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// Set defaults before calibrating the DDR2 buffer impendence
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// -Disable ODT
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// -Default drive strengths
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DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);
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// |=======================================================
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// |Auto calibrate the DDR2 buffers impendence
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// |=======================================================
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val32 = DmcReadReg(DMC_USER_STATUS_REG);
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while (!(val32 & 0x100)) {
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val32 = DmcReadReg(DMC_USER_STATUS_REG);
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}
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// Set the output driven strength
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DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 |
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(TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) |
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(TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) |
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(0x1 << TC_UIOHOCT_SHIFT) |
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(0x1 << TC_UIOHSTOP_SHIFT));
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// |======================================
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// | Set PL341 Feature Control Register
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// |======================================
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// | Disable early BRESP - use to optimise CLCD performance
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DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);
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//=================
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// Config memories
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//=================
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for (chip = 0; chip <= config-> max_chip; chip++) {
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// send nop
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);
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// pre-charge all
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
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// delay
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for (i = 0; i < 10; i++) {
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val32 = DmcReadReg(DMC_STATUS_REG);
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}
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// set (EMR2) extended mode register 2
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DmcWriteReg(DMC_DIRECT_CMD_REG,
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DMC_DIRECT_CMD_CHIP_ADDR(chip) |
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DMC_DIRECT_CMD_BANKADDR(2) |
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DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
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// set (EMR3) extended mode register 3
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DmcWriteReg(DMC_DIRECT_CMD_REG,
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DMC_DIRECT_CMD_CHIP_ADDR(chip) |
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DMC_DIRECT_CMD_BANKADDR(3) |
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DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
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// =================================
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// set (EMR) Extended Mode Register
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// ==================================
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// Put into OCD default state
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DmcWriteReg(DMC_DIRECT_CMD_REG,
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DMC_DIRECT_CMD_CHIP_ADDR(chip) |
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DMC_DIRECT_CMD_BANKADDR(1) |
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DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
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// ===========================================================
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// set (MR) mode register - With DLL reset
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// ===========================================================
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// Burst Length = 4 (010)
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// Burst Type = Seq (0)
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// Latency = 4 (100)
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// Test mode = Off (0)
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// DLL reset = Yes (1)
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// Wr Recovery = 4 (011)
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// PD = Normal (0)
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080742);
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// pre-charge all
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
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// auto-refresh
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
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// auto-refresh
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
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// delay
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for (i = 0; i < 10; i++) {
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val32 = DmcReadReg(DMC_STATUS_REG);
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}
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// ===========================================================
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// set (MR) mode register - Without DLL reset
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// ===========================================================
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// auto-refresh
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080642);
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// delay
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for (i = 0; i < 10; i++) {
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val32 = DmcReadReg(DMC_STATUS_REG);
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}
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// ======================================================
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// set (EMR) extended mode register - Enable OCD defaults
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// ======================================================
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val32 = 0; //NOP
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
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(DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) |
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DDR_EMR_RTT_75R |
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(DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
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// delay
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for (i = 0; i < 10; i++) {
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val32 = DmcReadReg(DMC_STATUS_REG);
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}
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// Set (EMR) extended mode register - OCD Exit
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val32 = 0; //NOP
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DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
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(DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) |
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DDR_EMR_RTT_75R |
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(DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
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}
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//----------------------------------------
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// go command
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DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);
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// wait for ready
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val32 = DmcReadReg(DMC_STATUS_REG);
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while (!(val32 & DMC_STATUS_READY)) {
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val32 = DmcReadReg(DMC_STATUS_REG);
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}
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}
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