Olivier Martin ec17f0f56a ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling ... See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in "Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions" Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524		2014-06-03 16:42:18 +00:00
..
Exception.c	ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling	2014-06-03 16:42:18 +00:00
ExceptionSupport.S	ARM Packages: Use .8byte instead of .dword for pointers	2014-05-08 14:59:50 +00:00
Mmu.c	ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-level	2014-05-14 05:32:07 +00:00