Olivier Martin ec17f0f56a ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling ... See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in "Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions" Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524		2014-06-03 16:42:18 +00:00
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Exception.c	ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling	2014-06-03 16:42:18 +00:00
ExceptionSupport.S	ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling	2014-06-03 16:42:18 +00:00
ExceptionSupport.asm	ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling	2014-06-03 16:42:18 +00:00
Mmu.c	ArmPkg/CpuDxe: Fixed the condition that checks if the level-1 descriptor points to a level-2 page table	2013-09-23 09:38:53 +00:00