mirror of https://github.com/acidanthera/audk.git
469 lines
15 KiB
C
469 lines
15 KiB
C
/** @file
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Serial I/O Port library functions with no library constructor/destructor
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Protocol/SerialIo.h>
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#include "PL011Uart.h"
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#define FRACTION_PART_SIZE_IN_BITS 6
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#define FRACTION_PART_MASK ((1 << FRACTION_PART_SIZE_IN_BITS) - 1)
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//
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// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only
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// control bit that is not supported.
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//
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STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
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/**
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Initialise the serial port to the specified settings.
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The serial port is re-configured only if the specified settings
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are different from the current settings.
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All unspecified settings will be set to the default values.
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@param UartBase The base address of the serial device.
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@param UartClkInHz The clock in Hz for the serial device.
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Ignored if the PCD PL011UartInteger is not 0
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@param BaudRate The baud rate of the serial device. If the
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baud rate is not supported, the speed will be
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reduced to the nearest supported one and the
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variable's value will be updated accordingly.
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@param ReceiveFifoDepth The number of characters the device will
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buffer on input. Value of 0 will use the
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device's default FIFO depth.
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@param Parity If applicable, this is the EFI_PARITY_TYPE
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that is computed or checked as each character
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is transmitted or received. If the device
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does not support parity, the value is the
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default parity value.
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@param DataBits The number of data bits in each character.
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@param StopBits If applicable, the EFI_STOP_BITS_TYPE number
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of stop bits per character.
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If the device does not support stop bits, the
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value is the default stop bit value.
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@retval RETURN_SUCCESS All attributes were set correctly on the
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serial device.
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@retval RETURN_INVALID_PARAMETER One or more of the attributes has an
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unsupported value.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartInitializePort (
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IN UINTN UartBase,
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IN UINT32 UartClkInHz,
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IN OUT UINT64 *BaudRate,
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IN OUT UINT32 *ReceiveFifoDepth,
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IN OUT EFI_PARITY_TYPE *Parity,
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IN OUT UINT8 *DataBits,
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IN OUT EFI_STOP_BITS_TYPE *StopBits
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)
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{
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UINT32 LineControl;
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UINT32 Divisor;
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UINT32 Integer;
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UINT32 Fractional;
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UINT32 HardwareFifoDepth;
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HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \
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> PL011_VER_R1P4) \
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? 32 : 16 ;
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// The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept
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// 1 char buffer as the minimum FIFO size. Because everything can be rounded
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// down, there is no maximum FIFO size.
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if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
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// Enable FIFO
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LineControl = PL011_UARTLCR_H_FEN;
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*ReceiveFifoDepth = HardwareFifoDepth;
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} else {
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// Disable FIFO
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LineControl = 0;
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// Nothing else to do. 1 byte FIFO is default.
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*ReceiveFifoDepth = 1;
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}
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//
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// Parity
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//
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switch (*Parity) {
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case DefaultParity:
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*Parity = NoParity;
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case NoParity:
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// Nothing to do. Parity is disabled by default.
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break;
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case EvenParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
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break;
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case OddParity:
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LineControl |= PL011_UARTLCR_H_PEN;
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break;
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case MarkParity:
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LineControl |= ( PL011_UARTLCR_H_PEN \
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| PL011_UARTLCR_H_SPS \
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| PL011_UARTLCR_H_EPS);
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break;
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case SpaceParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Data Bits
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//
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switch (*DataBits) {
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case 0:
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*DataBits = 8;
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case 8:
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LineControl |= PL011_UARTLCR_H_WLEN_8;
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break;
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case 7:
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LineControl |= PL011_UARTLCR_H_WLEN_7;
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break;
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case 6:
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LineControl |= PL011_UARTLCR_H_WLEN_6;
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break;
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case 5:
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LineControl |= PL011_UARTLCR_H_WLEN_5;
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Stop Bits
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//
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switch (*StopBits) {
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case DefaultStopBits:
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*StopBits = OneStopBit;
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case OneStopBit:
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// Nothing to do. One stop bit is enabled by default.
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break;
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case TwoStopBits:
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LineControl |= PL011_UARTLCR_H_STP2;
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break;
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case OneFiveStopBits:
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// Only 1 or 2 stop bits are supported
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default:
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return RETURN_INVALID_PARAMETER;
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}
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// Don't send the LineControl value to the PL011 yet,
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// wait until after the Baud Rate setting.
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// This ensures we do not mess up the UART settings halfway through
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// in the rare case when there is an error with the Baud Rate.
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//
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// Baud Rate
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//
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// If PL011 Integer value has been defined then always ignore the BAUD rate
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if (FixedPcdGet32 (PL011UartInteger) != 0) {
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Integer = FixedPcdGet32 (PL011UartInteger);
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Fractional = FixedPcdGet32 (PL011UartFractional);
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} else {
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// If BAUD rate is zero then replace it with the system default value
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if (*BaudRate == 0) {
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*BaudRate = FixedPcdGet32 (PcdSerialBaudRate);
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if (*BaudRate == 0) {
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return RETURN_INVALID_PARAMETER;
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}
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}
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if (0 == UartClkInHz) {
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return RETURN_INVALID_PARAMETER;
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}
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Divisor = (UartClkInHz * 4) / *BaudRate;
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Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
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Fractional = Divisor & FRACTION_PART_MASK;
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}
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//
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// If PL011 is already initialized, check the current settings
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// and re-initialize only if the settings are different.
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//
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if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
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(MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
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(MmioRead32 (UartBase + UARTIBRD) == Integer) &&
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(MmioRead32 (UartBase + UARTFBRD) == Fractional)) {
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// Nothing to do - already initialized with correct attributes
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return RETURN_SUCCESS;
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}
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// Wait for the end of transmission
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while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);
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// Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed
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// when the UART is enabled"
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MmioWrite32 (UartBase + UARTCR, 0);
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// Set Baud Rate Registers
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MmioWrite32 (UartBase + UARTIBRD, Integer);
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MmioWrite32 (UartBase + UARTFBRD, Fractional);
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// No parity, 1 stop, no fifo, 8 data bits
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MmioWrite32 (UartBase + UARTLCR_H, LineControl);
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// Clear any pending errors
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MmioWrite32 (UartBase + UARTECR, 0);
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// Enable Tx, Rx, and UART overall
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MmioWrite32 (UartBase + UARTCR,
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PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
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return RETURN_SUCCESS;
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}
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/**
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Assert or deassert the control signals on a serial port.
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The following control signals are set according their bit settings :
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. Request to Send
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. Data Terminal Ready
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@param[in] UartBase UART registers base address
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@param[in] Control The following bits are taken into account :
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. EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
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"Request To Send" control signal if this bit is
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equal to one/zero.
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. EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
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the "Data Terminal Ready" control signal if this
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bit is equal to one/zero.
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. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
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the hardware loopback if this bit is equal to
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one/zero.
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. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
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. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
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disable the hardware flow control based on CTS (Clear
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To Send) and RTS (Ready To Send) control signals.
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@retval RETURN_SUCCESS The new control bits were set on the device.
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@retval RETURN_UNSUPPORTED The device does not support this operation.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartSetControl (
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IN UINTN UartBase,
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IN UINT32 Control
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)
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{
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UINT32 Bits;
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if (Control & (mInvalidControlBits)) {
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return RETURN_UNSUPPORTED;
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}
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Bits = MmioRead32 (UartBase + UARTCR);
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if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
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Bits |= PL011_UARTCR_RTS;
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} else {
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Bits &= ~PL011_UARTCR_RTS;
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}
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if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {
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Bits |= PL011_UARTCR_DTR;
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} else {
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Bits &= ~PL011_UARTCR_DTR;
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}
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if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
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Bits |= PL011_UARTCR_LBE;
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} else {
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Bits &= ~PL011_UARTCR_LBE;
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}
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if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
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Bits |= (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);
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} else {
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Bits &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);
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}
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MmioWrite32 (UartBase + UARTCR, Bits);
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return RETURN_SUCCESS;
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}
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/**
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Retrieve the status of the control bits on a serial device.
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@param[in] UartBase UART registers base address
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@param[out] Control Status of the control bits on a serial device :
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. EFI_SERIAL_DATA_CLEAR_TO_SEND,
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EFI_SERIAL_DATA_SET_READY,
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EFI_SERIAL_RING_INDICATE,
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EFI_SERIAL_CARRIER_DETECT,
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EFI_SERIAL_REQUEST_TO_SEND,
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EFI_SERIAL_DATA_TERMINAL_READY
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are all related to the DTE (Data Terminal Equipment)
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and DCE (Data Communication Equipment) modes of
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operation of the serial device.
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. EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
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receive buffer is empty, 0 otherwise.
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. EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
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transmit buffer is empty, 0 otherwise.
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. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
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the hardware loopback is enabled (the output feeds the
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receive buffer), 0 otherwise.
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. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
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a loopback is accomplished by software, 0 otherwise.
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. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
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one if the hardware flow control based on CTS (Clear
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To Send) and RTS (Ready To Send) control signals is
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enabled, 0 otherwise.
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@retval RETURN_SUCCESS The control bits were read from the serial device.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartGetControl (
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IN UINTN UartBase,
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OUT UINT32 *Control
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)
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{
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UINT32 FlagRegister;
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UINT32 ControlRegister;
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FlagRegister = MmioRead32 (UartBase + UARTFR);
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ControlRegister = MmioRead32 (UartBase + UARTCR);
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*Control = 0;
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if ((FlagRegister & PL011_UARTFR_CTS) == PL011_UARTFR_CTS) {
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*Control |= EFI_SERIAL_CLEAR_TO_SEND;
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}
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if ((FlagRegister & PL011_UARTFR_DSR) == PL011_UARTFR_DSR) {
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*Control |= EFI_SERIAL_DATA_SET_READY;
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}
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if ((FlagRegister & PL011_UARTFR_RI) == PL011_UARTFR_RI) {
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*Control |= EFI_SERIAL_RING_INDICATE;
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}
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if ((FlagRegister & PL011_UARTFR_DCD) == PL011_UARTFR_DCD) {
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*Control |= EFI_SERIAL_CARRIER_DETECT;
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}
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if ((ControlRegister & PL011_UARTCR_RTS) == PL011_UARTCR_RTS) {
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*Control |= EFI_SERIAL_REQUEST_TO_SEND;
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}
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if ((ControlRegister & PL011_UARTCR_DTR) == PL011_UARTCR_DTR) {
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*Control |= EFI_SERIAL_DATA_TERMINAL_READY;
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}
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if ((FlagRegister & PL011_UARTFR_RXFE) == PL011_UARTFR_RXFE) {
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*Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
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}
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if ((FlagRegister & PL011_UARTFR_TXFE) == PL011_UARTFR_TXFE) {
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*Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
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}
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if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
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== (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {
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*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
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}
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if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {
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*Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
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}
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return RETURN_SUCCESS;
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}
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/**
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Write data to serial device.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Write data failed.
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@retval !0 Actual number of bytes written to serial device.
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**/
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UINTN
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EFIAPI
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PL011UartWrite (
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IN UINTN UartBase,
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IN UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINT8* CONST Final = &Buffer[NumberOfBytes];
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while (Buffer < Final) {
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// Wait until UART able to accept another char
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while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));
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MmioWrite8 (UartBase + UARTDR, *Buffer++);
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}
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return NumberOfBytes;
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}
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/**
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Read data from serial device and save the data in buffer.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Read data failed.
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@retval !0 Actual number of bytes read from serial device.
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**/
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UINTN
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EFIAPI
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PL011UartRead (
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IN UINTN UartBase,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINTN Count;
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for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
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while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
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*Buffer = MmioRead8 (UartBase + UARTDR);
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}
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return NumberOfBytes;
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}
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/**
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Check to see if any data is available to be read from the debug device.
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@retval TRUE At least one byte of data is available to be read
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@retval FALSE No data is available to be read
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**/
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BOOLEAN
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EFIAPI
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PL011UartPoll (
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IN UINTN UartBase
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)
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{
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return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
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}
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