mirror of https://github.com/acidanthera/audk.git
36dd3c781e
In certain HW implementation, the BIT7 of RTC Index register(0x70) is for NMI sources enable/disable but the BIT7 of 0x70 cannot be read before writing. Software which doesn't want to change the NMI sources enable/disable setting can write to the alias register 0x74, through which only BIT0 ~ BIT6 of 0x70 is modified. So two new PCDs are added so that platform can have the flexibility to change the default RTC register addresses from 0x70/0x71 to 0x74/0x75. With the new PCDs added, it can also support special HW that provides RTC storage in a different register pairs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> |
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| .. | ||
| PcRtc.c | ||
| PcRtc.h | ||
| PcRtc.uni | ||
| PcRtcEntry.c | ||
| PcRtcExtra.uni | ||
| PcatRealTimeClockRuntimeDxe.inf | ||