mirror of https://github.com/acidanthera/audk.git
81 lines
2.1 KiB
Plaintext
81 lines
2.1 KiB
Plaintext
/** @file
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SSDT Pci Osc (Operating System Capabilities)
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Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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- PCI Firmware Specification - Revision 3.3
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- ACPI 6.4 specification:
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- s6.2.13 "_PRT (PCI Routing Table)"
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- s6.1.1 "_ADR (Address)"
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- linux kernel code
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**/
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DefinitionBlock ("SsdtPciOsc.aml", "SSDT", 2, "ARMLTD", "PCI-OSC", 1) {
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// This table is just a template and is never installed as a table.
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// Pci devices are dynamically created at runtime as:
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// ASL:
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// Device (PCIx) {
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// ...
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// }
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// and the _OSC method available below is appended to the PCIx device as:
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// ASL:
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// Device (PCIx) {
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// ...
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// Method (_OSC, 4 {
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// ...
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// })
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// }
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Method (_OSC, 4) {
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//
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// OS Control Handoff
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//
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Name (SUPP, Zero) // PCI _OSC Support Field value
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Name (CTRL, Zero) // PCI _OSC Control Field value
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// Create DWord-addressable fields from the Capabilities Buffer
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CreateDWordField (Arg3, 0, CDW1)
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CreateDWordField (Arg3, 4, CDW2)
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CreateDWordField (Arg3, 8, CDW3)
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// Check for proper UUID
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If (LEqual (Arg0,ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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// Save Capabilities DWord2 & 3
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Store (CDW2, SUPP)
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Store (CDW3, CTRL)
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// Only allow native hot plug control if OS supports:
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// * ASPM
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// * Clock PM
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// * MSI/MSI-X
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If (LNotEqual (And (SUPP, 0x16), 0x16)) {
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And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits)
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}
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// Always allow native PME, AER (no dependencies)
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// Never allow SHPC (no SHPC controller in this system)
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And (CTRL, 0x1D, CTRL)
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If (LNotEqual (Arg1, One)) { // Unknown revision
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Or (CDW1, 0x08, CDW1)
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}
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If (LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked
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Or (CDW1, 0x10, CDW1)
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}
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// Update DWORD3 in the buffer
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Store (CTRL,CDW3)
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Return (Arg3)
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} Else {
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Or (CDW1, 4, CDW1) // Unrecognized UUID
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Return (Arg3)
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} // If
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} // _OSC
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}
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