audk/UefiCpuPkg/ResetVector/Vtf0
Zhiguang Liu db38c7de64 UefiCpuPkg/ResetVector: Remove AP waking vector from ResetVector
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4494

Current reset vector uses 0xffffffe0 as AP waking vector, and expects
GenFv generates code aligned on a 4k boundary which will jump to this
location. However, some issues are listed below
1. GenFV doesn't generate code as the comment expects, because GenFv
assumes no modifications are required to the VTF-0 'Volume Top File'.
2. Even if removing VFT0 signature and let GenFv to modify, Genfv is
hard-code using another flash address 0xffffffd0.
3. In the same patch series, AP waking vector code is removed from
GenFv, because no such usage anymore. The existing of first two issues
also approve the usage is not available for a long time.

Therefore, remove AP waking vector related code.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2023-09-18 02:39:25 +00:00
..
Ia16 UefiCpuPkg/ResetVector: Remove AP waking vector from ResetVector 2023-09-18 02:39:25 +00:00
Ia32
X64
CommonMacros.inc
DebugDisabled.asm
Main.asm
PageTables.inc
Port80Debug.asm
PostCodes.inc
ReadMe.txt UefiCpuPkg/ResetVector: Add guidance of FDF ffs rule 2023-06-27 10:16:25 +00:00
ResetVector.uni
ResetVectorExtra.uni
SerialDebug.asm
Vtf0.inf UefiCpuPkg/ResetVector: Remove pre-built binaries 2023-06-27 10:16:25 +00:00
Vtf0.nasmb

ReadMe.txt

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=== HOW TO USE VTF0 ===
Add this line to your DSC [Components.IA32] or [Components.X64] section:
  UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf

Add this line to your FDF FV section:
  INF  RuleOverride=RESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf

In your FDF FFS file rules sections add:
  [Rule.Common.SEC.RESET_VECTOR]
    FILE RAW = $(NAMED_GUID) {
      RAW BIN   |.bin
    }

=== VTF0 Boot Flow ===

1. Transition to IA32 flat mode
2. Locate BFV (Boot Firmware Volume) by checking every 4kb boundary
3. Locate SEC image
4. X64 VTF0 transitions to X64 mode
5. Call SEC image entry point

== VTF0 SEC input parameters ==

All inputs to SEC image are register based:
EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test)
DI      - 'BP': boot-strap processor, or 'AP': application processor
EBP/RBP - Pointer to the start of the Boot Firmware Volume