mirror of https://github.com/acidanthera/audk.git
273 lines
8.7 KiB
C
273 lines
8.7 KiB
C
/** @file
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Intel FSP Header File definition from Intel Firmware Support Package External
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Architecture Specification v2.0 and above.
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Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#ifndef __FSP_HEADER_FILE_H__
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#define __FSP_HEADER_FILE_H__
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#define FSP_HEADER_REVISION_3 3
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#define FSPE_HEADER_REVISION_1 1
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#define FSPP_HEADER_REVISION_1 1
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///
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/// Fixed FSP header offset in the FSP image
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///
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#define FSP_INFO_HEADER_OFF 0x94
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#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
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#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
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#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
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#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
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#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
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#define FSP_IA32 0
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#define FSP_X64 1
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#pragma pack(1)
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///
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/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
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///
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typedef struct {
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///
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/// Byte 0x00: Signature ('FSPH') for the FSP Information Header.
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///
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UINT32 Signature;
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///
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/// Byte 0x04: Length of the FSP Information Header.
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///
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UINT32 HeaderLength;
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///
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/// Byte 0x08: Reserved.
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///
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UINT8 Reserved1[2];
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///
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/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
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/// For revision v2.4 the value will be 0x24.
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///
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UINT8 SpecVersion;
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///
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/// Byte 0x0B: Revision of the FSP Information Header.
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/// The Current value for this field is 0x7.
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///
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UINT8 HeaderRevision;
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///
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/// Byte 0x0C: Revision of the FSP binary.
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/// Major.Minor.Revision.Build
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/// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:
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/// 7 : 0 - Build Number
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/// 15 : 8 - Revision
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/// 23 : 16 - Minor Version
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/// 31 : 24 - Major Version
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/// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision
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/// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.
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/// 7 : 0 - Low Byte of Build Number
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/// 15 : 8 - Low Byte of Revision
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/// 23 : 16 - Minor Version
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/// 31 : 24 - Major Version
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///
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UINT32 ImageRevision;
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///
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/// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.
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///
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CHAR8 ImageId[8];
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///
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/// Byte 0x18: Size of the entire FSP binary.
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///
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UINT32 ImageSize;
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///
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/// Byte 0x1C: FSP binary preferred base address.
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///
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UINT32 ImageBase;
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///
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/// Byte 0x20: Attribute for the FSP binary.
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/// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.
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/// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.
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/// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.
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/// Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP utilizes the FSP Variable Services defined in Section 9.6 to store non-volatile data. This bit is only valid if FSP HeaderRevision is >= 7.
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/// Bits 15:4 - Reserved
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///
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UINT16 ImageAttribute;
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///
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/// Byte 0x22: Attributes of the FSP Component.
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/// Bit 0 - Build Type
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/// 0 - Debug Build
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/// 1 - Release Build
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/// Bit 1 - Release Type
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/// 0 - Test Release
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/// 1 - Official Release
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/// Bit 11:2 - Reserved
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/// Bits 15:12 - Component Type
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/// 0000 - Reserved
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/// 0001 - FSP-T
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/// 0010 - FSP-M
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/// 0011 - FSP-S
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/// 0100 - FSP-I (FSP SMM)
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/// 0101 to 0111 - Reserved
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/// 1000 - FSP-O
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/// 1001 to 1111 - Reserved
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///
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UINT16 ComponentAttribute;
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///
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/// Byte 0x24: Offset of the FSP configuration region.
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///
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UINT32 CfgRegionOffset;
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///
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/// Byte 0x28: Size of the FSP configuration region.
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///
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UINT32 CfgRegionSize;
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///
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/// Byte 0x2C: Reserved2.
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///
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UINT32 Reserved2;
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///
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/// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.
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///
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UINT32 TempRamInitEntryOffset;
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///
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/// Byte 0x34: Reserved3.
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///
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UINT32 Reserved3;
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///
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/// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.
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///
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UINT32 NotifyPhaseEntryOffset;
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///
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/// Byte 0x3C: The offset for the API to initialize the memory.
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///
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UINT32 FspMemoryInitEntryOffset;
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///
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/// Byte 0x40: The offset for the API to tear down temporary RAM.
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///
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UINT32 TempRamExitEntryOffset;
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///
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/// Byte 0x44: The offset for the API to initialize the CPU and chipset.
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///
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UINT32 FspSiliconInitEntryOffset;
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///
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/// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.
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/// This value is only valid if FSP HeaderRevision is >= 5.
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/// If the value is set to 0x00000000, then this API is not available in this component.
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///
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UINT32 FspMultiPhaseSiInitEntryOffset;
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///
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/// Byte 0x4C: Extended revision of the FSP binary.
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/// This value is only valid if FSP HeaderRevision is >= 6.
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/// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.
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/// 7 : 0 - High Byte of Build Number
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/// 15 : 8 - High Byte of Revision
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/// The FSP binary build number can be decoded as follows:
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/// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]
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/// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
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/// Minor Version = ImageRevision[23:16]
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/// Major Version = ImageRevision[31:24]
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///
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UINT16 ExtendedImageRevision;
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///
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/// Byte 0x4E: Reserved4.
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///
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UINT16 Reserved4;
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///
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/// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.
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///
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UINT32 FspMultiPhaseMemInitEntryOffset;
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///
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/// Byte 0x54: Offset for the API to initialize SMM.
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///
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UINT32 FspSmmInitEntryOffset;
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} FSP_INFO_HEADER;
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///
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/// Signature of the FSP Extended Header
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///
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#define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')
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///
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/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.
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///
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typedef struct {
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///
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/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.
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///
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UINT32 Signature;
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///
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/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
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///
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UINT32 Length;
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///
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/// Byte 0x08: FSP producer defined revision of the table.
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///
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UINT8 Revision;
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///
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/// Byte 0x09: Reserved for future use.
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///
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UINT8 Reserved;
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///
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/// Byte 0x0A: FSP producer identification string
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///
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CHAR8 FspProducerId[6];
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///
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/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
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///
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UINT32 FspProducerRevision;
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///
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/// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
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///
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UINT32 FspProducerDataSize;
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///
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/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
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///
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} FSP_INFO_EXTENDED_HEADER;
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//
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// A generic table search algorithm for additional tables can be implemented with a
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// signature search algorithm until a terminator signature 'FSPP' is found.
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//
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#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')
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#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE
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///
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/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.
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///
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typedef struct {
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///
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/// Byte 0x00: FSP Patch Table Signature "FSPP".
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///
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UINT32 Signature;
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///
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/// Byte 0x04: Size including the PatchData.
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///
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UINT16 HeaderLength;
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///
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/// Byte 0x06: Revision is set to 0x01.
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///
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UINT8 HeaderRevision;
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///
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/// Byte 0x07: Reserved for future use.
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///
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UINT8 Reserved;
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///
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/// Byte 0x08: Number of entries to Patch.
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///
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UINT32 PatchEntryNum;
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///
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/// Byte 0x0C: Patch Data.
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///
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// UINT32 PatchData[];
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} FSP_PATCH_TABLE;
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#pragma pack()
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extern EFI_GUID gFspHeaderFileGuid;
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#endif
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