mirror of https://github.com/acidanthera/audk.git
534 lines
16 KiB
C
534 lines
16 KiB
C
/*++ @file
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Common definitions for UFS Host Controller Interface (UFSHCI)
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Copyright (c) Microsoft Corporation. All rights reserved.
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Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Revision Reference:
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JESD223 - Universal Flash Storage Host Controller Interface (UFSHCI)
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Version 2.0
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https://www.jedec.org/system/files/docs/JESD223C.pdf
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--*/
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#ifndef __UFS_HCI_H__
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#define __UFS_HCI_H__
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#include <Base.h>
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#include <IndustryStandard/Ufs.h>
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//
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// Host Capabilities Register Offsets
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//
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#define UFS_HC_CAP_OFFSET 0x0000 // Controller Capabilities
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#define UFS_HC_VER_OFFSET 0x0008 // Version
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#define UFS_HC_DDID_OFFSET 0x0010 // Device ID and Device Class
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#define UFS_HC_PMID_OFFSET 0x0014 // Product ID and Manufacturer ID
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#define UFS_HC_AHIT_OFFSET 0x0018 // Auto-Hibernate Idle Timer
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//
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// Operation and Runtime Register Offsets
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//
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#define UFS_HC_IS_OFFSET 0x0020 // Interrupt Status
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#define UFS_HC_IE_OFFSET 0x0024 // Interrupt Enable
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#define UFS_HC_STATUS_OFFSET 0x0030 // Host Controller Status
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#define UFS_HC_ENABLE_OFFSET 0x0034 // Host Controller Enable
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#define UFS_HC_UECPA_OFFSET 0x0038 // Host UIC Error Code PHY Adapter Layer
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#define UFS_HC_UECDL_OFFSET 0x003c // Host UIC Error Code Data Link Layer
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#define UFS_HC_UECN_OFFSET 0x0040 // Host UIC Error Code Network Layer
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#define UFS_HC_UECT_OFFSET 0x0044 // Host UIC Error Code Transport Layer
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#define UFS_HC_UECDME_OFFSET 0x0048 // Host UIC Error Code DME
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#define UFS_HC_UTRIACR_OFFSET 0x004c // UTP Transfer Request Interrupt Aggregation Control Register
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//
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// UTP Transfer Register Offsets
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//
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#define UFS_HC_UTRLBA_OFFSET 0x0050 // UTP Transfer Request List Base Address
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#define UFS_HC_UTRLBAU_OFFSET 0x0054 // UTP Transfer Request List Base Address Upper 32-Bits
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#define UFS_HC_UTRLDBR_OFFSET 0x0058 // UTP Transfer Request List Door Bell Register
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#define UFS_HC_UTRLCLR_OFFSET 0x005c // UTP Transfer Request List CLear Register
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#define UFS_HC_UTRLRSR_OFFSET 0x0060 // UTP Transfer Request Run-Stop Register
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//
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// UTP Task Management Register Offsets
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//
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#define UFS_HC_UTMRLBA_OFFSET 0x0070 // UTP Task Management Request List Base Address
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#define UFS_HC_UTMRLBAU_OFFSET 0x0074 // UTP Task Management Request List Base Address Upper 32-Bits
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#define UFS_HC_UTMRLDBR_OFFSET 0x0078 // UTP Task Management Request List Door Bell Register
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#define UFS_HC_UTMRLCLR_OFFSET 0x007c // UTP Task Management Request List CLear Register
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#define UFS_HC_UTMRLRSR_OFFSET 0x0080 // UTP Task Management Run-Stop Register
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//
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// UIC Command Register Offsets
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//
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#define UFS_HC_UIC_CMD_OFFSET 0x0090 // UIC Command Register
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#define UFS_HC_UCMD_ARG1_OFFSET 0x0094 // UIC Command Argument 1
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#define UFS_HC_UCMD_ARG2_OFFSET 0x0098 // UIC Command Argument 2
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#define UFS_HC_UCMD_ARG3_OFFSET 0x009c // UIC Command Argument 3
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//
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// UMA Register Offsets
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//
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#define UFS_HC_UMA_OFFSET 0x00b0 // Reserved for Unified Memory Extension
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#define UFS_HC_HCE_EN BIT0
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#define UFS_HC_HCS_DP BIT0
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#define UFS_HC_HCS_UCRDY BIT3
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#define UFS_HC_IS_ULSS BIT8
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#define UFS_HC_IS_UCCS BIT10
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#define UFS_HC_CAP_64ADDR BIT24
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#define UFS_HC_CAP_NUTMRS (BIT16 | BIT17 | BIT18)
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#define UFS_HC_CAP_NUTRS (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)
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#define UFS_HC_UTMRLRSR BIT0
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#define UFS_HC_UTRLRSR BIT0
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//
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// The initial value of the OCS field of UTP TRD or TMRD descriptor
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// defined in JEDEC JESD223 specification
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//
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#define UFS_HC_TRD_OCS_INIT_VALUE 0x0F
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//
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// A maximum of length of 256KB is supported by PRDT entry
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//
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#define UFS_MAX_DATA_LEN_PER_PRD 0x40000
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#define UFS_STORAGE_COMMAND_TYPE 0x01
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#define UFS_REGULAR_COMMAND 0x00
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#define UFS_INTERRUPT_COMMAND 0x01
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#pragma pack(1)
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//
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// UFSHCI 2.0 Spec Section 5.2.1 Offset 00h: CAP - Controller Capabilities
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//
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typedef struct {
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UINT8 Nutrs : 4; // Number of UTP Transfer Request Slots
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UINT8 Rsvd1 : 4;
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UINT8 NoRtt; // Number of outstanding READY TO TRANSFER (RTT) requests supported
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UINT8 Nutmrs : 3; // Number of UTP Task Management Request Slots
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UINT8 Rsvd2 : 4;
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UINT8 AutoHs : 1; // Auto-Hibernation Support
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UINT8 As64 : 1; // 64-bit addressing supported
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UINT8 Oodds : 1; // Out of order data delivery supported
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UINT8 UicDmetms : 1; // UIC DME_TEST_MODE command supported
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UINT8 Ume : 1; // Reserved for Unified Memory Extension
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UINT8 Rsvd4 : 4;
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} UFS_HC_CAP;
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//
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// UFSHCI 2.0 Spec Section 5.2.2 Offset 08h: VER - UFS Version
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//
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typedef struct {
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UINT8 Vs : 4; // Version Suffix
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UINT8 Mnr : 4; // Minor version number
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UINT8 Mjr; // Major version number
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UINT16 Rsvd1;
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} UFS_HC_VER;
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//
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// UFSHCI 2.0 Spec Section 5.2.3 Offset 10h: HCPID - Host Controller Product ID
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//
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#define UFS_HC_PID UINT32
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//
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// UFSHCI 2.0 Spec Section 5.2.4 Offset 14h: HCMID - Host Controller Manufacturer ID
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//
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#define UFS_HC_MID UINT32
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//
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// UFSHCI 2.0 Spec Section 5.2.5 Offset 18h: AHIT - Auto-Hibernate Idle Timer
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//
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typedef struct {
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UINT32 Ahitv : 10; // Auto-Hibernate Idle Timer Value
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UINT32 Ts : 3; // Timer scale
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UINT32 Rsvd1 : 19;
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} UFS_HC_AHIT;
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//
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// UFSHCI 2.0 Spec Section 5.3.1 Offset 20h: IS - Interrupt Status
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//
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typedef struct {
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UINT16 Utrcs : 1; // UTP Transfer Request Completion Status
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UINT16 Udepri : 1; // UIC DME_ENDPOINT_RESET Indication
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UINT16 Ue : 1; // UIC Error
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UINT16 Utms : 1; // UIC Test Mode Status
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UINT16 Upms : 1; // UIC Power Mode Status
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UINT16 Uhxs : 1; // UIC Hibernate Exit Status
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UINT16 Uhes : 1; // UIC Hibernate Enter Status
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UINT16 Ulls : 1; // UIC Link Lost Status
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UINT16 Ulss : 1; // UIC Link Startup Status
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UINT16 Utmrcs : 1; // UTP Task Management Request Completion Status
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UINT16 Uccs : 1; // UIC Command Completion Status
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UINT16 Dfes : 1; // Device Fatal Error Status
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UINT16 Utpes : 1; // UTP Error Status
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UINT16 Rsvd1 : 3;
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UINT16 Hcfes : 1; // Host Controller Fatal Error Status
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UINT16 Sbfes : 1; // System Bus Fatal Error Status
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UINT16 Rsvd2 : 14;
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} UFS_HC_IS;
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//
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// UFSHCI 2.0 Spec Section 5.3.2 Offset 24h: IE - Interrupt Enable
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//
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typedef struct {
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UINT16 Utrce : 1; // UTP Transfer Request Completion Enable
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UINT16 Udeprie : 1; // UIC DME_ENDPOINT_RESET Enable
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UINT16 Uee : 1; // UIC Error Enable
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UINT16 Utmse : 1; // UIC Test Mode Status Enable
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UINT16 Upmse : 1; // UIC Power Mode Status Enable
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UINT16 Uhxse : 1; // UIC Hibernate Exit Status Enable
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UINT16 Uhese : 1; // UIC Hibernate Enter Status Enable
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UINT16 Ullse : 1; // UIC Link Lost Status Enable
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UINT16 Ulsse : 1; // UIC Link Startup Status Enable
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UINT16 Utmrce : 1; // UTP Task Management Request Completion Enable
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UINT16 Ucce : 1; // UIC Command Completion Enable
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UINT16 Dfee : 1; // Device Fatal Error Enable
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UINT16 Utpee : 1; // UTP Error Enable
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UINT16 Rsvd1 : 3;
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UINT16 Hcfee : 1; // Host Controller Fatal Error Enable
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UINT16 Sbfee : 1; // System Bus Fatal Error Enable
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UINT16 Rsvd2 : 14;
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} UFS_HC_IE;
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//
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// UFSHCI 2.0 Spec Section 5.3.3 Offset 30h: HCS - Host Controller Status
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//
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typedef struct {
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UINT8 Dp : 1; // Device Present
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UINT8 UtrlRdy : 1; // UTP Transfer Request List Ready
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UINT8 UtmrlRdy : 1; // UTP Task Management Request List Ready
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UINT8 UcRdy : 1; // UIC COMMAND Ready
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UINT8 Rsvd1 : 4;
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UINT8 Upmcrs : 3; // UIC Power Mode Change Request Status
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UINT8 Rsvd2 : 1; // UIC Hibernate Exit Status Enable
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UINT8 Utpec : 4; // UTP Error Code
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UINT8 TtagUtpE; // Task Tag of UTP error
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UINT8 TlunUtpE; // Target LUN of UTP error
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} UFS_HC_STATUS;
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//
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// UFSHCI 2.0 Spec Section 5.3.4 Offset 34h: HCE - Host Controller Enable
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//
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typedef struct {
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UINT32 Hce : 1; // Host Controller Enable
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UINT32 Rsvd1 : 31;
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} UFS_HC_ENABLE;
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//
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// UFSHCI 2.0 Spec Section 5.3.5 Offset 38h: UECPA - Host UIC Error Code PHY Adapter Layer
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//
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typedef struct {
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UINT32 Ec : 5; // UIC PHY Adapter Layer Error Code
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UINT32 Rsvd1 : 26;
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UINT32 Err : 1; // UIC PHY Adapter Layer Error
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} UFS_HC_UECPA;
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//
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// UFSHCI 2.0 Spec Section 5.3.6 Offset 3ch: UECDL - Host UIC Error Code Data Link Layer
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//
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typedef struct {
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UINT32 Ec : 15; // UIC Data Link Layer Error Code
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UINT32 Rsvd1 : 16;
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UINT32 Err : 1; // UIC Data Link Layer Error
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} UFS_HC_UECDL;
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//
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// UFSHCI 2.0 Spec Section 5.3.7 Offset 40h: UECN - Host UIC Error Code Network Layer
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//
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typedef struct {
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UINT32 Ec : 3; // UIC Network Layer Error Code
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UINT32 Rsvd1 : 28;
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UINT32 Err : 1; // UIC Network Layer Error
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} UFS_HC_UECN;
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//
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// UFSHCI 2.0 Spec Section 5.3.8 Offset 44h: UECT - Host UIC Error Code Transport Layer
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//
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typedef struct {
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UINT32 Ec : 7; // UIC Transport Layer Error Code
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UINT32 Rsvd1 : 24;
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UINT32 Err : 1; // UIC Transport Layer Error
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} UFS_HC_UECT;
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//
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// UFSHCI 2.0 Spec Section 5.3.9 Offset 48h: UECDME - Host UIC Error Code
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//
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typedef struct {
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UINT32 Ec : 1; // UIC DME Error Code
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UINT32 Rsvd1 : 30;
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UINT32 Err : 1; // UIC DME Error
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} UFS_HC_UECDME;
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//
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// UFSHCI 2.0 Spec Section 5.3.10 Offset 4Ch: UTRIACR - UTP Transfer Request Interrupt Aggregation Control Register
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//
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typedef struct {
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UINT8 IaToVal; // Interrupt aggregation timeout value
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UINT8 IacTh : 5; // Interrupt aggregation counter threshold
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UINT8 Rsvd1 : 3;
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UINT8 Ctr : 1; // Counter and Timer Reset
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UINT8 Rsvd2 : 3;
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UINT8 Iasb : 1; // Interrupt aggregation status bit
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UINT8 Rsvd3 : 3;
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UINT8 IapwEn : 1; // Interrupt aggregation parameter write enable
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UINT8 Rsvd4 : 6;
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UINT8 IaEn : 1; // Interrupt Aggregation Enable/Disable
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} UFS_HC_UTRIACR;
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//
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// UFSHCI 2.0 Spec Section 5.4.1 Offset 50h: UTRLBA - UTP Transfer Request List Base Address
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//
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typedef struct {
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UINT32 Rsvd1 : 10;
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UINT32 UtrlBa : 22; // UTP Transfer Request List Base Address
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} UFS_HC_UTRLBA;
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//
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// UFSHCI 2.0 Spec Section 5.4.2 Offset 54h: UTRLBAU - UTP Transfer Request List Base Address Upper 32-bits
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//
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#define UFS_HC_UTRLBAU UINT32
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//
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// UFSHCI 2.0 Spec Section 5.4.3 Offset 58h: UTRLDBR - UTP Transfer Request List Door Bell Register
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//
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#define UFS_HC_UTRLDBR UINT32
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//
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// UFSHCI 2.0 Spec Section 5.4.4 Offset 5Ch: UTRLCLR - UTP Transfer Request List CLear Register
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//
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#define UFS_HC_UTRLCLR UINT32
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#if 0
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//
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// UFSHCI 2.0 Spec Section 5.4.5 Offset 60h: UTRLRSR - UTP Transfer Request List Run Stop Register
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//
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typedef struct {
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UINT32 UtrlRsr : 1; // UTP Transfer Request List Run-Stop Register
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UINT32 Rsvd1 : 31;
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} UFS_HC_UTRLRSR;
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#endif
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//
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// UFSHCI 2.0 Spec Section 5.5.1 Offset 70h: UTMRLBA - UTP Task Management Request List Base Address
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//
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typedef struct {
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UINT32 Rsvd1 : 10;
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UINT32 UtmrlBa : 22; // UTP Task Management Request List Base Address
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} UFS_HC_UTMRLBA;
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//
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// UFSHCI 2.0 Spec Section 5.5.2 Offset 74h: UTMRLBAU - UTP Task Management Request List Base Address Upper 32-bits
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//
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#define UFS_HC_UTMRLBAU UINT32
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//
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// UFSHCI 2.0 Spec Section 5.5.3 Offset 78h: UTMRLDBR - UTP Task Management Request List Door Bell Register
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//
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typedef struct {
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UINT32 UtmrlDbr : 8; // UTP Task Management Request List Door bell Register
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UINT32 Rsvd1 : 24;
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} UFS_HC_UTMRLDBR;
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//
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// UFSHCI 2.0 Spec Section 5.5.4 Offset 7Ch: UTMRLCLR - UTP Task Management Request List CLear Register
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//
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typedef struct {
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UINT32 UtmrlClr : 8; // UTP Task Management List Clear Register
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UINT32 Rsvd1 : 24;
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} UFS_HC_UTMRLCLR;
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#if 0
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//
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// UFSHCI 2.0 Spec Section 5.5.5 Offset 80h: UTMRLRSR - UTP Task Management Request List Run Stop Register
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//
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typedef struct {
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UINT32 UtmrlRsr : 1; // UTP Task Management Request List Run-Stop Register
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UINT32 Rsvd1 : 31;
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} UFS_HC_UTMRLRSR;
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#endif
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//
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// UFSHCI 2.0 Spec Section 5.6.1 Offset 90h: UICCMD - UIC Command
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//
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typedef struct {
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UINT32 CmdOp : 8; // Command Opcode
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UINT32 Rsvd1 : 24;
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} UFS_HC_UICCMD;
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//
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// UFSHCI 2.0 Spec Section 5.6.2 Offset 94h: UICCMDARG1 - UIC Command Argument 1
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//
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#define UFS_HC_UICCMD_ARG1 UINT32
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//
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// UFSHCI 2.0 Spec Section 5.6.2 Offset 98h: UICCMDARG2 - UIC Command Argument 2
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//
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#define UFS_HC_UICCMD_ARG2 UINT32
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//
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// UFSHCI 2.0 Spec Section 5.6.2 Offset 9ch: UICCMDARG3 - UIC Command Argument 3
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//
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#define UFS_HC_UICCMD_ARG3 UINT32
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//
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// UIC command opcodes
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//
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typedef enum {
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UfsUicDmeGet = 0x01,
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UfsUicDmeSet = 0x02,
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UfsUicDmePeerGet = 0x03,
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UfsUicDmePeerSet = 0x04,
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UfsUicDmePwrOn = 0x10,
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UfsUicDmePwrOff = 0x11,
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UfsUicDmeEnable = 0x12,
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UfsUicDmeReset = 0x14,
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UfsUicDmeEndpointReset = 0x15,
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UfsUicDmeLinkStartup = 0x16,
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UfsUicDmeHibernateEnter = 0x17,
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UfsUicDmeHibernateExit = 0x18,
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UfsUicDmeTestMode = 0x1A
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} UFS_UIC_OPCODE;
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//
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// UFSHCI 2.0 Spec Section 6.1.1 - UTP Transfer Request Descriptor
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//
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typedef struct {
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//
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// DW0
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//
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UINT32 Rsvd1 : 24;
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UINT32 Int : 1; /* Interrupt */
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UINT32 Dd : 2; /* Data Direction */
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UINT32 Rsvd2 : 1;
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UINT32 Ct : 4; /* Command Type */
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//
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// DW1
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//
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UINT32 Rsvd3;
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//
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// DW2
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//
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UINT32 Ocs : 8; /* Overall Command Status */
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UINT32 Rsvd4 : 24;
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//
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// DW3
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//
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UINT32 Rsvd5;
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//
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// DW4
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//
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UINT32 Rsvd6 : 7;
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UINT32 UcdBa : 25; /* UTP Command Descriptor Base Address */
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//
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// DW5
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//
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UINT32 UcdBaU; /* UTP Command Descriptor Base Address Upper 32-bits */
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//
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// DW6
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//
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UINT16 RuL; /* Response UPIU Length */
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UINT16 RuO; /* Response UPIU Offset */
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//
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// DW7
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//
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UINT16 PrdtL; /* PRDT Length */
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UINT16 PrdtO; /* PRDT Offset */
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} UTP_TRD;
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typedef enum {
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UfsNoData = 0,
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UfsDataOut = 1,
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UfsDataIn = 2,
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UfsDdReserved
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} UFS_DATA_DIRECTION;
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typedef struct {
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//
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// DW0
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//
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UINT32 Rsvd1 : 2;
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UINT32 DbAddr : 30; /* Data Base Address */
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//
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// DW1
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//
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UINT32 DbAddrU; /* Data Base Address Upper 32-bits */
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//
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// DW2
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//
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UINT32 Rsvd2;
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//
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// DW3
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//
|
|
UINT32 DbCount : 18; /* Data Byte Count */
|
|
UINT32 Rsvd3 : 14;
|
|
} UTP_TR_PRD;
|
|
|
|
//
|
|
// UFSHCI 2.0 Spec Section 6.2.1 - UTP Task Management Request Descriptor
|
|
//
|
|
typedef struct {
|
|
//
|
|
// DW0
|
|
//
|
|
UINT32 Rsvd1 : 24;
|
|
UINT32 Int : 1; /* Interrupt */
|
|
UINT32 Rsvd2 : 7;
|
|
|
|
//
|
|
// DW1
|
|
//
|
|
UINT32 Rsvd3;
|
|
|
|
//
|
|
// DW2
|
|
//
|
|
UINT32 Ocs : 8; /* Overall Command Status */
|
|
UINT32 Rsvd4 : 24;
|
|
|
|
//
|
|
// DW3
|
|
//
|
|
UINT32 Rsvd5;
|
|
|
|
//
|
|
// DW4 - DW11
|
|
//
|
|
UTP_TM_REQ_UPIU TmReq; /* Task Management Request UPIU */
|
|
|
|
//
|
|
// DW12 - DW19
|
|
//
|
|
UTP_TM_RESP_UPIU TmResp; /* Task Management Response UPIU */
|
|
} UTP_TMRD;
|
|
|
|
#pragma pack()
|
|
|
|
#endif
|