mirror of https://github.com/acidanthera/audk.git
275d0a39c4
BSP workflow is quite simliar to the non-coco case. TDX_WORK_AREA_PGTBL_READY is used to record the paging mode: 1 == 4-level paging 2 == 5-level paging APs will look at TDX_WORK_AREA_PGTBL_READY to figure whenever they should enable 5-level paging or not. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240301074402.98625-9-kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: move "CheckForSev:" label into "%if PG_5_LEVEL" scope, as discussed with Gerd] Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Oliver Steffen <osteffen@redhat.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Tom Lendacky <thomas.lendacky@amd.com> [lersek@redhat.com: turn the "Cc:" message headers from Gerd's on-list posting into "Cc:" tags in the commit message, in order to pacify "PatchCheck.py"] |
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AmdSev.asm | ||
Flat32ToFlat64.asm | ||
IntelTdx.asm | ||
PageTables64.asm |