audk/OvmfPkg/ResetVector/Ia32
Gerd Hoffmann 275d0a39c4 OvmfPkg/ResetVector: wire up 5-level paging for TDX
BSP workflow is quite simliar to the non-coco case.

TDX_WORK_AREA_PGTBL_READY is used to record the paging mode:
  1 == 4-level paging
  2 == 5-level paging

APs will look at TDX_WORK_AREA_PGTBL_READY to figure whenever
they should enable 5-level paging or not.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20240301074402.98625-9-kraxel@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
[lersek@redhat.com: move "CheckForSev:" label into "%if PG_5_LEVEL" scope,
 as discussed with Gerd]
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Oliver Steffen <osteffen@redhat.com>
Cc: Michael Roth <michael.roth@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
[lersek@redhat.com: turn the "Cc:" message headers from Gerd's on-list
 posting into "Cc:" tags in the commit message, in order to pacify
 "PatchCheck.py"]
2024-03-01 18:47:27 +00:00
..
AmdSev.asm OvmfPkg/ResetVector: split SEV and non-CoCo workflows 2024-03-01 18:47:27 +00:00
Flat32ToFlat64.asm OvmfPkg/ResetVector: Fix assembler bit test flag check 2023-07-14 22:52:58 +00:00
IntelTdx.asm OvmfPkg/ResetVector: wire up 5-level paging for TDX 2024-03-01 18:47:27 +00:00
PageTables64.asm OvmfPkg/ResetVector: wire up 5-level paging for TDX 2024-03-01 18:47:27 +00:00