mirror of https://github.com/acidanthera/audk.git
119 lines
4.0 KiB
C
119 lines
4.0 KiB
C
/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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/*
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* This function configures the all interrupts to be Non-secure.
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*
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*/
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VOID
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EFIAPI
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ArmGicSetupNonSecure (
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IN UINTN MpId,
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN InterruptId;
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UINTN CachedPriorityMask;
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UINTN Index;
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CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
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// Check if there are any pending interrupts
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//TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
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while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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// Write to End of interrupt signal
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
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}
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// Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
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if (IS_PRIMARY_CORE(MpId)) {
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// Ensure all GIC interrupts are Non-Secure
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for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
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}
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} else {
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// The secondary cores only set the Non Secure bit to their banked PPIs
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
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}
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// Ensure all interrupts can get through the priority mask
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
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}
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/*
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* This function configures the interrupts set by the mask to be secure.
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*
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*/
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VOID
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EFIAPI
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ArmGicSetSecureInterrupts (
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IN UINTN GicDistributorBase,
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IN UINTN* GicSecureInterruptMask,
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IN UINTN GicSecureInterruptMaskSize
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)
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{
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UINTN Index;
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UINT32 InterruptStatus;
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// We must not have more interrupts defined by the mask than the number of available interrupts
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ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
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// Set all the interrupts defined by the mask as Secure
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for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
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InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
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}
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}
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VOID
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EFIAPI
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ArmGicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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// Set Priority Mask to allow interrupts
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
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// Enable CPU interface in Secure world
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// Enable CPU inteface in Non-secure World
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// Signal Secure Interrupts to CPU using FIQ line *
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
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ARM_GIC_ICCICR_ENABLE_SECURE |
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ARM_GIC_ICCICR_ENABLE_NS |
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ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
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}
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VOID
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EFIAPI
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ArmGicEnableDistributor (
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IN INTN GicDistributorBase
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)
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{
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// Turn on the GIC distributor
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
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}
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