mirror of https://github.com/acidanthera/audk.git
657 lines
20 KiB
C
657 lines
20 KiB
C
/** @file
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* File managing the MMU for ARMv8 architecture
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*
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* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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* Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Uefi.h>
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#include <Chipset/AArch64.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmMmuLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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STATIC
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UINT64
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ArmMemoryAttributeToPageAttribute (
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IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
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)
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{
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switch (Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
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return TT_ATTR_INDX_MEMORY_WRITE_BACK;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
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// Uncached and device mappings are treated as outer shareable by default,
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
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default:
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ASSERT (0);
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
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if (ArmReadCurrentEL () == AARCH64_EL2)
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return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
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else
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return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
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}
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}
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#define MIN_T0SZ 16
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#define BITS_PER_LEVEL 9
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#define MAX_VA_BITS 48
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STATIC
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UINTN
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GetRootTableEntryCount (
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IN UINTN T0SZ
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)
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{
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return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
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}
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STATIC
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UINTN
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GetRootTableLevel (
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IN UINTN T0SZ
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)
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{
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return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
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}
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STATIC
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VOID
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ReplaceTableEntry (
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IN UINT64 *Entry,
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IN UINT64 Value,
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IN UINT64 RegionStart,
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IN BOOLEAN IsLiveBlockMapping
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)
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{
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if (!ArmMmuEnabled () || !IsLiveBlockMapping) {
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*Entry = Value;
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ArmUpdateTranslationTableEntry (Entry, (VOID *)(UINTN)RegionStart);
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} else {
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ArmReplaceLiveTranslationEntry (Entry, Value, RegionStart);
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}
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}
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STATIC
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VOID
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FreePageTablesRecursive (
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IN UINT64 *TranslationTable,
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IN UINTN Level
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)
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{
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UINTN Index;
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ASSERT (Level <= 3);
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if (Level < 3) {
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for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
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if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
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FreePageTablesRecursive ((VOID *)(UINTN)(TranslationTable[Index] &
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TT_ADDRESS_MASK_BLOCK_ENTRY),
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Level + 1);
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}
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}
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}
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FreePages (TranslationTable, 1);
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}
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STATIC
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BOOLEAN
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IsBlockEntry (
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IN UINT64 Entry,
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IN UINTN Level
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)
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{
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if (Level == 3) {
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return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3;
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}
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return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY;
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}
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STATIC
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BOOLEAN
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IsTableEntry (
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IN UINT64 Entry,
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IN UINTN Level
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)
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{
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if (Level == 3) {
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//
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// TT_TYPE_TABLE_ENTRY aliases TT_TYPE_BLOCK_ENTRY_LEVEL3
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// so we need to take the level into account as well.
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//
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return FALSE;
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}
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return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY;
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}
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STATIC
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EFI_STATUS
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UpdateRegionMappingRecursive (
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IN UINT64 RegionStart,
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IN UINT64 RegionEnd,
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IN UINT64 AttributeSetMask,
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IN UINT64 AttributeClearMask,
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IN UINT64 *PageTable,
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IN UINTN Level
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)
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{
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UINTN BlockShift;
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UINT64 BlockMask;
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UINT64 BlockEnd;
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UINT64 *Entry;
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UINT64 EntryValue;
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VOID *TranslationTable;
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EFI_STATUS Status;
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ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
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BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ;
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BlockMask = MAX_UINT64 >> BlockShift;
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DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTION__,
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Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask));
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for (; RegionStart < RegionEnd; RegionStart = BlockEnd) {
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BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
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Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
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//
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// If RegionStart or BlockEnd is not aligned to the block size at this
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// level, we will have to create a table mapping in order to map less
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// than a block, and recurse to create the block or page entries at
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// the next level. No block mappings are allowed at all at level 0,
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// so in that case, we have to recurse unconditionally.
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// If we are changing a table entry and the AttributeClearMask is non-zero,
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// we cannot replace it with a block entry without potentially losing
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// attribute information, so keep the table entry in that case.
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//
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if (Level == 0 || ((RegionStart | BlockEnd) & BlockMask) != 0 ||
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(IsTableEntry (*Entry, Level) && AttributeClearMask != 0)) {
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ASSERT (Level < 3);
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if (!IsTableEntry (*Entry, Level)) {
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//
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// No table entry exists yet, so we need to allocate a page table
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// for the next level.
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//
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TranslationTable = AllocatePages (1);
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if (TranslationTable == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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if (!ArmMmuEnabled ()) {
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//
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// Make sure we are not inadvertently hitting in the caches
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// when populating the page tables.
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//
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InvalidateDataCacheRange (TranslationTable, EFI_PAGE_SIZE);
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}
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ZeroMem (TranslationTable, EFI_PAGE_SIZE);
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if (IsBlockEntry (*Entry, Level)) {
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//
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// We are splitting an existing block entry, so we have to populate
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// the new table with the attributes of the block entry it replaces.
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//
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Status = UpdateRegionMappingRecursive (RegionStart & ~BlockMask,
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(RegionStart | BlockMask) + 1, *Entry & TT_ATTRIBUTES_MASK,
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0, TranslationTable, Level + 1);
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if (EFI_ERROR (Status)) {
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//
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// The range we passed to UpdateRegionMappingRecursive () is block
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// aligned, so it is guaranteed that no further pages were allocated
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// by it, and so we only have to free the page we allocated here.
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//
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FreePages (TranslationTable, 1);
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return Status;
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}
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}
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} else {
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TranslationTable = (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOCK_ENTRY);
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}
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//
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// Recurse to the next level
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//
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Status = UpdateRegionMappingRecursive (RegionStart, BlockEnd,
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AttributeSetMask, AttributeClearMask, TranslationTable,
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Level + 1);
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if (EFI_ERROR (Status)) {
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if (!IsTableEntry (*Entry, Level)) {
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//
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// We are creating a new table entry, so on failure, we can free all
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// allocations we made recursively, given that the whole subhierarchy
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// has not been wired into the live page tables yet. (This is not
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// possible for existing table entries, since we cannot revert the
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// modifications we made to the subhierarchy it represents.)
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//
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FreePageTablesRecursive (TranslationTable, Level + 1);
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}
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return Status;
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}
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if (!IsTableEntry (*Entry, Level)) {
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EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;
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ReplaceTableEntry (Entry, EntryValue, RegionStart,
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IsBlockEntry (*Entry, Level));
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}
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} else {
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EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
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EntryValue |= RegionStart;
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EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
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: TT_TYPE_BLOCK_ENTRY;
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if (IsTableEntry (*Entry, Level)) {
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//
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// We are replacing a table entry with a block entry. This is only
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// possible if we are keeping none of the original attributes.
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// We can free the table entry's page table, and all the ones below
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// it, since we are dropping the only possible reference to it.
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//
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ASSERT (AttributeClearMask == 0);
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TranslationTable = (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOCK_ENTRY);
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ReplaceTableEntry (Entry, EntryValue, RegionStart, TRUE);
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FreePageTablesRecursive (TranslationTable, Level + 1);
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} else {
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ReplaceTableEntry (Entry, EntryValue, RegionStart, FALSE);
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}
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}
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}
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return EFI_SUCCESS;
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}
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STATIC
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EFI_STATUS
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UpdateRegionMapping (
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IN UINT64 RegionStart,
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IN UINT64 RegionLength,
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IN UINT64 AttributeSetMask,
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IN UINT64 AttributeClearMask
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)
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{
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UINTN T0SZ;
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if (((RegionStart | RegionLength) & EFI_PAGE_MASK)) {
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return EFI_INVALID_PARAMETER;
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}
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T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
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return UpdateRegionMappingRecursive (RegionStart, RegionStart + RegionLength,
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AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (),
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GetRootTableLevel (T0SZ));
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}
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STATIC
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EFI_STATUS
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FillTranslationTable (
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IN UINT64 *RootTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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return UpdateRegionMapping (
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MemoryRegion->VirtualBase,
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MemoryRegion->Length,
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ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,
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0
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);
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}
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STATIC
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UINT64
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GcdAttributeToPageAttribute (
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IN UINT64 GcdAttributes
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)
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{
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UINT64 PageAttributes;
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switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
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case EFI_MEMORY_UC:
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PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
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break;
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case EFI_MEMORY_WC:
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PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
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break;
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case EFI_MEMORY_WT:
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PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
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break;
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case EFI_MEMORY_WB:
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PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
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break;
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default:
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PageAttributes = TT_ATTR_INDX_MASK;
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break;
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}
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if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||
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(GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {
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if (ArmReadCurrentEL () == AARCH64_EL2) {
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PageAttributes |= TT_XN_MASK;
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} else {
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PageAttributes |= TT_UXN_MASK | TT_PXN_MASK;
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}
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}
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if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
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PageAttributes |= TT_AP_RO_RO;
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}
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return PageAttributes | TT_AF;
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}
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EFI_STATUS
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ArmSetMemoryAttributes (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes
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)
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{
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UINT64 PageAttributes;
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UINT64 PageAttributeMask;
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PageAttributes = GcdAttributeToPageAttribute (Attributes);
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PageAttributeMask = 0;
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if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {
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//
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// No memory type was set in Attributes, so we are going to update the
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// permissions only.
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//
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PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
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PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |
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TT_PXN_MASK | TT_XN_MASK);
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}
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return UpdateRegionMapping (BaseAddress, Length, PageAttributes,
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PageAttributeMask);
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}
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STATIC
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EFI_STATUS
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SetMemoryRegionAttribute (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes,
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IN UINT64 BlockEntryMask
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)
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{
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return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask);
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}
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EFI_STATUS
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ArmSetMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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UINT64 Val;
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if (ArmReadCurrentEL () == AARCH64_EL1) {
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Val = TT_PXN_MASK | TT_UXN_MASK;
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} else {
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Val = TT_XN_MASK;
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}
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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Val,
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~TT_ADDRESS_MASK_BLOCK_ENTRY);
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}
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EFI_STATUS
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ArmClearMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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UINT64 Mask;
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// XN maps to UXN in the EL1&0 translation regime
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Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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0,
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Mask);
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}
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EFI_STATUS
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ArmSetMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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TT_AP_RO_RO,
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~TT_ADDRESS_MASK_BLOCK_ENTRY);
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}
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EFI_STATUS
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ArmClearMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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TT_AP_RW_RW,
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~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
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}
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EFI_STATUS
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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VOID* TranslationTable;
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UINTN MaxAddressBits;
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UINT64 MaxAddress;
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UINTN T0SZ;
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UINTN RootTableEntryCount;
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UINT64 TCR;
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EFI_STATUS Status;
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if (MemoryTable == NULL) {
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ASSERT (MemoryTable != NULL);
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return EFI_INVALID_PARAMETER;
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}
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//
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// Limit the virtual address space to what we can actually use: UEFI
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// mandates a 1:1 mapping, so no point in making the virtual address
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// space larger than the physical address space. We also have to take
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// into account the architectural limitations that result from UEFI's
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// use of 4 KB pages.
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//
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MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS);
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MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
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T0SZ = 64 - MaxAddressBits;
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RootTableEntryCount = GetRootTableEntryCount (T0SZ);
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//
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// Set TCR that allows us to retrieve T0SZ in the subsequent functions
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//
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// Ideally we will be running at EL2, but should support EL1 as well.
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// UEFI should not run at EL3.
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if (ArmReadCurrentEL () == AARCH64_EL2) {
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//Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
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TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
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// Set the Physical Address Size using MaxAddress
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if (MaxAddress < SIZE_4GB) {
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TCR |= TCR_PS_4GB;
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} else if (MaxAddress < SIZE_64GB) {
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TCR |= TCR_PS_64GB;
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} else if (MaxAddress < SIZE_1TB) {
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TCR |= TCR_PS_1TB;
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} else if (MaxAddress < SIZE_4TB) {
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TCR |= TCR_PS_4TB;
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} else if (MaxAddress < SIZE_16TB) {
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TCR |= TCR_PS_16TB;
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} else if (MaxAddress < SIZE_256TB) {
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TCR |= TCR_PS_256TB;
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} else {
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DEBUG ((DEBUG_ERROR,
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"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
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MaxAddress));
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ASSERT (0); // Bigger than 48-bit memory space are not supported
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return EFI_UNSUPPORTED;
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}
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} else if (ArmReadCurrentEL () == AARCH64_EL1) {
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// Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
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TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
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// Set the Physical Address Size using MaxAddress
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if (MaxAddress < SIZE_4GB) {
|
|
TCR |= TCR_IPS_4GB;
|
|
} else if (MaxAddress < SIZE_64GB) {
|
|
TCR |= TCR_IPS_64GB;
|
|
} else if (MaxAddress < SIZE_1TB) {
|
|
TCR |= TCR_IPS_1TB;
|
|
} else if (MaxAddress < SIZE_4TB) {
|
|
TCR |= TCR_IPS_4TB;
|
|
} else if (MaxAddress < SIZE_16TB) {
|
|
TCR |= TCR_IPS_16TB;
|
|
} else if (MaxAddress < SIZE_256TB) {
|
|
TCR |= TCR_IPS_256TB;
|
|
} else {
|
|
DEBUG ((DEBUG_ERROR,
|
|
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
|
|
MaxAddress));
|
|
ASSERT (0); // Bigger than 48-bit memory space are not supported
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
} else {
|
|
ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
|
|
//
|
|
// Translation table walks are always cache coherent on ARMv8-A, so cache
|
|
// maintenance on page tables is never needed. Since there is a risk of
|
|
// loss of coherency when using mismatched attributes, and given that memory
|
|
// is mapped cacheable except for extraordinary cases (such as non-coherent
|
|
// DMA), have the page table walker perform cached accesses as well, and
|
|
// assert below that that matches the attributes we use for CPU accesses to
|
|
// the region.
|
|
//
|
|
TCR |= TCR_SH_INNER_SHAREABLE |
|
|
TCR_RGN_OUTER_WRITE_BACK_ALLOC |
|
|
TCR_RGN_INNER_WRITE_BACK_ALLOC;
|
|
|
|
// Set TCR
|
|
ArmSetTCR (TCR);
|
|
|
|
// Allocate pages for translation table
|
|
TranslationTable = AllocatePages (1);
|
|
if (TranslationTable == NULL) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
//
|
|
// We set TTBR0 just after allocating the table to retrieve its location from
|
|
// the subsequent functions without needing to pass this value across the
|
|
// functions. The MMU is only enabled after the translation tables are
|
|
// populated.
|
|
//
|
|
ArmSetTTBR0 (TranslationTable);
|
|
|
|
if (TranslationTableBase != NULL) {
|
|
*TranslationTableBase = TranslationTable;
|
|
}
|
|
|
|
if (TranslationTableSize != NULL) {
|
|
*TranslationTableSize = RootTableEntryCount * sizeof (UINT64);
|
|
}
|
|
|
|
//
|
|
// Make sure we are not inadvertently hitting in the caches
|
|
// when populating the page tables.
|
|
//
|
|
InvalidateDataCacheRange (TranslationTable,
|
|
RootTableEntryCount * sizeof (UINT64));
|
|
ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));
|
|
|
|
while (MemoryTable->Length != 0) {
|
|
Status = FillTranslationTable (TranslationTable, MemoryTable);
|
|
if (EFI_ERROR (Status)) {
|
|
goto FreeTranslationTable;
|
|
}
|
|
MemoryTable++;
|
|
}
|
|
|
|
//
|
|
// EFI_MEMORY_UC ==> MAIR_ATTR_DEVICE_MEMORY
|
|
// EFI_MEMORY_WC ==> MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE
|
|
// EFI_MEMORY_WT ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH
|
|
// EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
|
|
//
|
|
ArmSetMAIR (
|
|
MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
|
|
MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) |
|
|
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) |
|
|
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
|
|
);
|
|
|
|
ArmDisableAlignmentCheck ();
|
|
ArmEnableStackAlignmentCheck ();
|
|
ArmEnableInstructionCache ();
|
|
ArmEnableDataCache ();
|
|
|
|
ArmEnableMmu ();
|
|
return EFI_SUCCESS;
|
|
|
|
FreeTranslationTable:
|
|
FreePages (TranslationTable, 1);
|
|
return Status;
|
|
}
|
|
|
|
RETURN_STATUS
|
|
EFIAPI
|
|
ArmMmuBaseLibConstructor (
|
|
VOID
|
|
)
|
|
{
|
|
extern UINT32 ArmReplaceLiveTranslationEntrySize;
|
|
|
|
//
|
|
// The ArmReplaceLiveTranslationEntry () helper function may be invoked
|
|
// with the MMU off so we have to ensure that it gets cleaned to the PoC
|
|
//
|
|
WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
|
|
ArmReplaceLiveTranslationEntrySize);
|
|
|
|
return RETURN_SUCCESS;
|
|
}
|