mirror of https://github.com/acidanthera/audk.git
f4c845e46b
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
\-> PDPTE[1] --> PDE[0-255]
If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as writable, today's logic doesn't inherit the
parent entry's attributes when determining the child entry's
attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit.
But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only.
The change fixes the bug.
If the inheritable attributes in ParentPagingEntry conflicts with the
requested attributes, let the child entries take the parent attributes
and loosen the attribute in the parent entry.
E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as
ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change
PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first.
Then change PDE[0].ReadWrite = 1.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
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|---|---|---|
| .. | ||
| BaseUefiCpuLib | ||
| BaseXApicLib | ||
| BaseXApicX2ApicLib | ||
| CpuCacheInfoLib | ||
| CpuCommonFeaturesLib | ||
| CpuExceptionHandlerLib | ||
| CpuPageTableLib | ||
| CpuTimerLib | ||
| MicrocodeLib | ||
| MpInitLib | ||
| MpInitLibUp | ||
| MtrrLib | ||
| PlatformSecLibNull | ||
| RegisterCpuFeaturesLib | ||
| SecPeiDxeTimerLibUefiCpu | ||
| SmmCpuFeaturesLib | ||
| SmmCpuPlatformHookLibNull | ||
| SmmCpuRendezvousLib | ||
| VmgExitLibNull | ||