mirror of https://github.com/acidanthera/audk.git
286 lines
8.1 KiB
NASM
286 lines
8.1 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Sets the CR3 register for 64-bit paging
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2017 - 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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; common for all levels
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%define PAGE_PRESENT 0x01
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%define PAGE_READ_WRITE 0x02
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%define PAGE_USER_SUPERVISOR 0x04
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%define PAGE_WRITE_THROUGH 0x08
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%define PAGE_CACHE_DISABLE 0x010
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%define PAGE_ACCESSED 0x020
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%define PAGE_DIRTY 0x040
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%define PAGE_GLOBAL 0x0100
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; page table entries (level 1)
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%define PAGE_PTE_PAT 0x080
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; page directory entries (level 2+)
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%define PAGE_PDE_LARGEPAGE 0x080
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%define PAGE_PDE_PAT 0x01000
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%define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDE_LARGEPAGE_ATTR (PAGE_PDE_LARGEPAGE + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDE_DIRECTORY_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define TDX_BSP 1
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%define TDX_AP 2
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%define TDX_AP_5_LEVEL 3
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;
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; For OVMF, build some initial page tables at
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; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
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;
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; This range should match with PcdOvmfSecPageTablesSize which is
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; declared in the FDF files.
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;
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; At the end of PEI, the pages tables will be rebuilt into a
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; more permanent location by DxeIpl.
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;
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%macro ClearOvmfPageTables 0
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mov ecx, 6 * 0x1000 / 4
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xor eax, eax
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.clearPageTablesMemoryLoop:
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mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
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loop .clearPageTablesMemoryLoop
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%endmacro
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;
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; Create page tables for 4-level paging
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;
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; Argument: upper 32 bits of the leaf page table entries
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;
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%macro CreatePageTables4Level 1
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; indicate 4-level paging
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debugShowPostCode 0x41
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (4)], 0
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1004)], 0
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x100C)], 0
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1014)], 0
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x101C)], 0
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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.pageTableEntriesLoop4Level:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_PDE_LARGEPAGE_ATTR
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mov dword[ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov dword[(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], %1
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loop .pageTableEntriesLoop4Level
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%endmacro
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;
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; Check whenever 5-level paging can be used
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;
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; Argument: jump label for 4-level paging
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;
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%macro Check5LevelPaging 1
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; check for cpuid leaf 0x07
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mov eax, 0x00
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cpuid
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cmp eax, 0x07
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jb %1
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; check for la57 (aka 5-level paging)
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mov eax, 0x07
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mov ecx, 0x00
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cpuid
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bt ecx, 16
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jnc %1
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; check for cpuid leaf 0x80000001
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb %1
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; check for 1g pages
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mov eax, 0x80000001
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cpuid
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bt edx, 26
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jnc %1
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%endmacro
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;
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; Create page tables for 5-level paging with gigabyte pages
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;
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; Argument: upper 32 bits of the leaf page table entries
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;
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; We have 6 pages available for the early page tables,
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; we use four of them:
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; PT_ADDR(0) - level 5 directory
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; PT_ADDR(0x1000) - level 4 directory
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; PT_ADDR(0x2000) - level 2 directory (0 -> 1GB)
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; PT_ADDR(0x3000) - level 3 directory
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;
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; The level 2 directory for the first gigabyte has the same
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; physical address in both 4-level and 5-level paging mode,
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; SevClearPageEncMaskForGhcbPage depends on this.
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;
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; The 1 GB -> 4 GB range is mapped using 1G pages in the
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; level 3 directory.
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;
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%macro CreatePageTables5Level 1
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; indicate 5-level paging
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debugShowPostCode 0x51
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; level 5
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (4)], 0
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; level 4
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1004)], 0
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; level 3 (1x -> level 2, 3x 1GB)
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mov dword[PT_ADDR (0x3000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x3004)], 0
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mov dword[PT_ADDR (0x3008)], (1 << 30) + PAGE_PDE_LARGEPAGE_ATTR
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mov dword[PT_ADDR (0x300c)], %1
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mov dword[PT_ADDR (0x3010)], (2 << 30) + PAGE_PDE_LARGEPAGE_ATTR
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mov dword[PT_ADDR (0x3014)], %1
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mov dword[PT_ADDR (0x3018)], (3 << 30) + PAGE_PDE_LARGEPAGE_ATTR
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mov dword[PT_ADDR (0x301c)], %1
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;
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; level 2 (512 * 2MB entries => 1GB)
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;
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mov ecx, 0x200
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.pageTableEntriesLoop5Level:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_PDE_LARGEPAGE_ATTR
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mov dword[ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov dword[(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], %1
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loop .pageTableEntriesLoop5Level
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%endmacro
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%macro Enable5LevelPaging 0
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; set la57 bit in cr4
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mov eax, cr4
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bts eax, 12
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mov cr4, eax
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%endmacro
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;
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; Modified: EAX, EBX, ECX, EDX
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;
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SetCr3ForPageTables64:
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; Check the TDX features.
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; If it is TDX APs, then jump to SetCr3 directly.
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; In TD guest the initialization is done by BSP, including building
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; the page tables. APs will spin on until byte[TDX_WORK_AREA_PGTBL_READY]
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; is set.
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OneTimeCall CheckTdxFeaturesBeforeBuildPagetables
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cmp eax, TDX_BSP
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je TdxBspInit
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cmp eax, TDX_AP
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je SetCr3
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%if PG_5_LEVEL
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cmp eax, TDX_AP_5_LEVEL
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jne CheckForSev
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Enable5LevelPaging
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jmp SetCr3
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CheckForSev:
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%endif
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; Check whether the SEV is active and populate the SevEsWorkArea
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OneTimeCall CheckSevFeatures
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cmp byte[WORK_AREA_GUEST_TYPE], 1
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jz SevInit
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;
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; normal (non-CoCo) workflow
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;
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ClearOvmfPageTables
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%if PG_5_LEVEL
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Check5LevelPaging Paging4Level
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CreatePageTables5Level 0
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Enable5LevelPaging
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jmp SetCr3
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Paging4Level:
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%endif
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CreatePageTables4Level 0
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jmp SetCr3
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SevInit:
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;
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; SEV workflow
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;
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ClearOvmfPageTables
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; If SEV is enabled, the C-bit position is always above 31.
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; The mask will be saved in the EDX and applied during the
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; the page table build below.
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OneTimeCall GetSevCBitMaskAbove31
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CreatePageTables4Level edx
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; Clear the C-bit from the GHCB page if the SEV-ES is enabled.
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OneTimeCall SevClearPageEncMaskForGhcbPage
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jmp SetCr3
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TdxBspInit:
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;
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; TDX BSP workflow
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;
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ClearOvmfPageTables
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%if PG_5_LEVEL
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Check5LevelPaging Tdx4Level
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CreatePageTables5Level 0
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OneTimeCall TdxPostBuildPageTables5Level
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Enable5LevelPaging
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jmp SetCr3
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Tdx4Level:
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%endif
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CreatePageTables4Level 0
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OneTimeCall TdxPostBuildPageTables
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jmp SetCr3
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SetCr3:
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;
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; common workflow
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;
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; Set CR3 now that the paging structures are available
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;
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mov eax, PT_ADDR (0)
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mov cr3, eax
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OneTimeCallRet SetCr3ForPageTables64
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