mirror of https://github.com/acidanthera/audk.git
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/** @file
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HstiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <IndustryStandard/Hsti.h>
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#include <IndustryStandard/Q35MchIch9.h>
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#include "VirtHstiDxe.h"
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STATIC VIRT_ADAPTER_INFO_PLATFORM_SECURITY mHstiQ35 = {
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PLATFORM_SECURITY_VERSION_VNEXTCS,
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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{ L"OVMF (Qemu Q35)" },
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VIRT_HSTI_SECURITY_FEATURE_SIZE,
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};
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VIRT_ADAPTER_INFO_PLATFORM_SECURITY *
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VirtHstiQemuQ35Init (
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VOID
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)
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{
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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VirtHstiSetSupported (&mHstiQ35, 0, VIRT_HSTI_BYTE0_SMM_SMRAM_LOCK);
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VirtHstiSetSupported (&mHstiQ35, 0, VIRT_HSTI_BYTE0_SMM_SECURE_VARS_FLASH);
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}
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return &mHstiQ35;
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}
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VOID
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VirtHstiQemuQ35Verify (
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VOID
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)
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{
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if (VirtHstiIsSupported (&mHstiQ35, 0, VIRT_HSTI_BYTE0_SMM_SMRAM_LOCK)) {
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CHAR16 *ErrorMsg = NULL;
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UINT8 SmramVal;
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UINT8 EsmramcVal;
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SmramVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_SMRAM));
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EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
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if (!(EsmramcVal & MCH_ESMRAMC_T_EN)) {
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ErrorMsg = L"q35 smram access is open";
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} else if (!(SmramVal & MCH_SMRAM_D_LCK)) {
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ErrorMsg = L"q35 smram config is not locked";
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}
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VirtHstiTestResult (ErrorMsg, 0, VIRT_HSTI_BYTE0_SMM_SMRAM_LOCK);
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}
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if (VirtHstiIsSupported (&mHstiQ35, 0, VIRT_HSTI_BYTE0_SMM_SECURE_VARS_FLASH)) {
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CHAR16 *ErrorMsg = NULL;
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switch (VirtHstiQemuFirmwareFlashCheck (PcdGet32 (PcdOvmfFlashNvStorageVariableBase))) {
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case QEMU_FIRMWARE_FLASH_WRITABLE:
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ErrorMsg = L"qemu vars pflash is not secure";
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break;
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}
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VirtHstiTestResult (ErrorMsg, 0, VIRT_HSTI_BYTE0_SMM_SECURE_VARS_FLASH);
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}
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}
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