mirror of https://github.com/acidanthera/audk.git
249 lines
8.1 KiB
C
249 lines
8.1 KiB
C
/* $NetBSD: mca_machdep.h,v 1.1 2006/04/07 14:21:18 cherry Exp $ */
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/*-
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* Copyright (c) 2002 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_MCA_H_
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#define _MACHINE_MCA_H_
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struct mca_record_header {
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uint64_t rh_seqnr; /* Record id. */
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uint8_t rh_major; /* BCD (=02). */
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uint8_t rh_minor; /* BCD (=00). */
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uint8_t rh_error; /* Error severity. */
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#define MCA_RH_ERROR_RECOVERABLE 0
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#define MCA_RH_ERROR_FATAL 1
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#define MCA_RH_ERROR_CORRECTED 2
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uint8_t rh_flags;
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#define MCA_RH_FLAGS_PLATFORM_ID 0x01 /* Platform_id present. */
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uint32_t rh_length; /* Size including header. */
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uint8_t rh_time[8];
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#define MCA_RH_TIME_SEC 0
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#define MCA_RH_TIME_MIN 1
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#define MCA_RH_TIME_HOUR 2
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#define MCA_RH_TIME_MDAY 4
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#define MCA_RH_TIME_MON 5
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#define MCA_RH_TIME_YEAR 6
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#define MCA_RH_TIME_CENT 7
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struct uuid rh_platform;
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};
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struct mca_section_header {
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struct uuid sh_uuid;
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uint8_t sh_major; /* BCD (=02). */
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uint8_t sh_minor; /* BCD (=00). */
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uint8_t sh_flags;
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#define MCA_SH_FLAGS_CORRECTED 0x01 /* Error has been corrected. */
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#define MCA_SH_FLAGS_PROPAGATE 0x02 /* Possible propagation. */
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#define MCA_SH_FLAGS_RESET 0x04 /* Reset device before use. */
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#define MCA_SH_FLAGS_VALID 0x80 /* Flags are valid. */
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uint8_t __reserved;
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uint32_t sh_length; /* Size including header. */
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};
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struct mca_cpu_record {
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uint64_t cpu_flags;
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#define MCA_CPU_FLAGS_ERRMAP (1ULL << 0)
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#define MCA_CPU_FLAGS_STATE (1ULL << 1)
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#define MCA_CPU_FLAGS_CR_LID (1ULL << 2)
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#define MCA_CPU_FLAGS_PSI_STRUCT (1ULL << 3)
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#define MCA_CPU_FLAGS_CACHE(x) (((x) >> 4) & 15)
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#define MCA_CPU_FLAGS_TLB(x) (((x) >> 8) & 15)
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#define MCA_CPU_FLAGS_BUS(x) (((x) >> 12) & 15)
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#define MCA_CPU_FLAGS_REG(x) (((x) >> 16) & 15)
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#define MCA_CPU_FLAGS_MS(x) (((x) >> 20) & 15)
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#define MCA_CPU_FLAGS_CPUID (1ULL << 24)
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uint64_t cpu_errmap;
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uint64_t cpu_state;
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uint64_t cpu_cr_lid;
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/* Nx cpu_mod (cache). */
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/* Nx cpu_mod (TLB). */
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/* Nx cpu_mod (bus). */
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/* Nx cpu_mod (reg). */
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/* Nx cpu_mod (MS). */
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/* cpu_cpuid. */
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/* cpu_psi. */
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};
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struct mca_cpu_cpuid {
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uint64_t cpuid[6];
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};
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struct mca_cpu_mod {
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uint64_t cpu_mod_flags;
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#define MCA_CPU_MOD_FLAGS_INFO (1ULL << 0)
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#define MCA_CPU_MOD_FLAGS_REQID (1ULL << 1)
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#define MCA_CPU_MOD_FLAGS_RSPID (1ULL << 2)
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#define MCA_CPU_MOD_FLAGS_TGTID (1ULL << 3)
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#define MCA_CPU_MOD_FLAGS_IP (1ULL << 4)
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uint64_t cpu_mod_info;
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uint64_t cpu_mod_reqid;
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uint64_t cpu_mod_rspid;
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uint64_t cpu_mod_tgtid;
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uint64_t cpu_mod_ip;
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};
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struct mca_cpu_psi {
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uint64_t cpu_psi_flags;
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#define MCA_CPU_PSI_FLAGS_STATE (1ULL << 0)
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#define MCA_CPU_PSI_FLAGS_BR (1ULL << 1)
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#define MCA_CPU_PSI_FLAGS_CR (1ULL << 2)
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#define MCA_CPU_PSI_FLAGS_AR (1ULL << 3)
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#define MCA_CPU_PSI_FLAGS_RR (1ULL << 4)
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#define MCA_CPU_PSI_FLAGS_FR (1ULL << 5)
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uint8_t cpu_psi_state[1024]; /* XXX variable? */
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uint64_t cpu_psi_br[8];
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uint64_t cpu_psi_cr[128]; /* XXX variable? */
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uint64_t cpu_psi_ar[128]; /* XXX variable? */
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uint64_t cpu_psi_rr[8];
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uint64_t cpu_psi_fr[256]; /* 16 bytes per register! */
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};
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struct mca_mem_record {
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uint64_t mem_flags;
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#define MCA_MEM_FLAGS_STATUS (1ULL << 0)
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#define MCA_MEM_FLAGS_ADDR (1ULL << 1)
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#define MCA_MEM_FLAGS_ADDRMASK (1ULL << 2)
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#define MCA_MEM_FLAGS_NODE (1ULL << 3)
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#define MCA_MEM_FLAGS_CARD (1ULL << 4)
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#define MCA_MEM_FLAGS_MODULE (1ULL << 5)
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#define MCA_MEM_FLAGS_BANK (1ULL << 6)
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#define MCA_MEM_FLAGS_DEVICE (1ULL << 7)
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#define MCA_MEM_FLAGS_ROW (1ULL << 8)
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#define MCA_MEM_FLAGS_COLUMN (1ULL << 9)
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#define MCA_MEM_FLAGS_BITPOS (1ULL << 10)
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#define MCA_MEM_FLAGS_REQID (1ULL << 11)
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#define MCA_MEM_FLAGS_RSPID (1ULL << 12)
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#define MCA_MEM_FLAGS_TGTID (1ULL << 13)
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#define MCA_MEM_FLAGS_BUSDATA (1ULL << 14)
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#define MCA_MEM_FLAGS_OEM_ID (1ULL << 15)
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#define MCA_MEM_FLAGS_OEM_DATA (1ULL << 16)
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uint64_t mem_status;
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uint64_t mem_addr;
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uint64_t mem_addrmask;
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uint16_t mem_node;
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uint16_t mem_card;
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uint16_t mem_module;
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uint16_t mem_bank;
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uint16_t mem_device;
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uint16_t mem_row;
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uint16_t mem_column;
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uint16_t mem_bitpos;
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uint64_t mem_reqid;
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uint64_t mem_rspid;
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uint64_t mem_tgtid;
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uint64_t mem_busdata;
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struct uuid mem_oem_id;
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uint16_t mem_oem_length; /* Size of OEM data. */
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/* N bytes of OEM platform data. */
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};
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struct mca_pcibus_record {
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uint64_t pcibus_flags;
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#define MCA_PCIBUS_FLAGS_STATUS (1ULL << 0)
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#define MCA_PCIBUS_FLAGS_ERROR (1ULL << 1)
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#define MCA_PCIBUS_FLAGS_BUS (1ULL << 2)
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#define MCA_PCIBUS_FLAGS_ADDR (1ULL << 3)
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#define MCA_PCIBUS_FLAGS_DATA (1ULL << 4)
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#define MCA_PCIBUS_FLAGS_CMD (1ULL << 5)
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#define MCA_PCIBUS_FLAGS_REQID (1ULL << 6)
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#define MCA_PCIBUS_FLAGS_RSPID (1ULL << 7)
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#define MCA_PCIBUS_FLAGS_TGTID (1ULL << 8)
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#define MCA_PCIBUS_FLAGS_OEM_ID (1ULL << 9)
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#define MCA_PCIBUS_FLAGS_OEM_DATA (1ULL << 10)
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uint64_t pcibus_status;
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uint16_t pcibus_error;
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uint16_t pcibus_bus;
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uint32_t __reserved;
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uint64_t pcibus_addr;
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uint64_t pcibus_data;
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uint64_t pcibus_cmd;
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uint64_t pcibus_reqid;
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uint64_t pcibus_rspid;
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uint64_t pcibus_tgtid;
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struct uuid pcibus_oem_id;
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uint16_t pcibus_oem_length; /* Size of OEM data. */
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/* N bytes of OEM platform data. */
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};
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struct mca_pcidev_record {
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uint64_t pcidev_flags;
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#define MCA_PCIDEV_FLAGS_STATUS (1ULL << 0)
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#define MCA_PCIDEV_FLAGS_INFO (1ULL << 1)
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#define MCA_PCIDEV_FLAGS_REG_MEM (1ULL << 2)
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#define MCA_PCIDEV_FLAGS_REG_IO (1ULL << 3)
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#define MCA_PCIDEV_FLAGS_REG_DATA (1ULL << 4)
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#define MCA_PCIDEV_FLAGS_OEM_DATA (1ULL << 5)
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uint64_t pcidev_status;
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struct {
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uint16_t info_vendor;
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uint16_t info_device;
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uint32_t info_ccfn; /* Class code & funct. nr. */
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#define MCA_PCIDEV_INFO_CLASS(x) ((x) & 0xffffff)
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#define MCA_PCIDEV_INFO_FUNCTION(x) (((x) >> 24) & 0xff)
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uint8_t info_slot;
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uint8_t info_bus;
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uint8_t info_segment;
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uint8_t __res0;
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uint32_t __res1;
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} pcidev_info;
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uint32_t pcidev_reg_mem;
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uint32_t pcidev_reg_io;
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/* Nx pcidev_reg. */
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/* M bytes of OEM platform data. */
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};
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struct mca_pcidev_reg {
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uint64_t pcidev_reg_addr;
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uint64_t pcidev_reg_data;
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};
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#define MCA_UUID_CPU \
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{0xe429faf1,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
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#define MCA_UUID_MEMORY \
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{0xe429faf2,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
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#define MCA_UUID_SEL \
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{0xe429faf3,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
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#define MCA_UUID_PCI_BUS \
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{0xe429faf4,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
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#define MCA_UUID_SMBIOS \
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{0xe429faf5,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
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#define MCA_UUID_PCI_DEV \
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{0xe429faf6,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
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#define MCA_UUID_GENERIC \
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{0xe429faf7,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}
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#ifdef _KERNEL
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void ia64_mca_init(void);
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void ia64_mca_save_state(int);
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#endif /* _KERNEL */
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#endif /* _MACHINE_MCA_H_ */
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