mirror of https://github.com/acidanthera/audk.git
231 lines
6.2 KiB
NASM
231 lines
6.2 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT ArmInvalidateInstructionCache
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EXPORT ArmInvalidateDataCacheEntryByMVA
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EXPORT ArmCleanDataCacheEntryByMVA
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EXPORT ArmCleanInvalidateDataCacheEntryByMVA
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EXPORT ArmInvalidateDataCacheEntryBySetWay
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EXPORT ArmCleanDataCacheEntryBySetWay
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EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
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EXPORT ArmDrainWriteBuffer
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EXPORT ArmEnableMmu
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EXPORT ArmDisableMmu
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EXPORT ArmMmuEnabled
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EXPORT ArmEnableDataCache
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EXPORT ArmDisableDataCache
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EXPORT ArmEnableInstructionCache
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EXPORT ArmDisableInstructionCache
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EXPORT ArmEnableBranchPrediction
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EXPORT ArmDisableBranchPrediction
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EXPORT ArmV7AllDataCachesOperation
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EXPORT ArmDataMemoryBarrier
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EXPORT ArmDataSyncronizationBarrier
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EXPORT ArmInstructionSynchronizationBarrier
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AREA ArmCacheLib, CODE, READONLY
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PRESERVE8
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DC_ON EQU ( 0x1:SHL:2 )
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IC_ON EQU ( 0x1:SHL:12 )
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ArmInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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dsb
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isb
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bx lr
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ArmInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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dsb
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isb
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bx lr
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ArmInvalidateInstructionCache
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mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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isb
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bx LR
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ArmEnableMmu
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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dsb
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isb
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bx LR
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ArmMmuEnabled
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ArmDisableMmu
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0 ;Disable MMU
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mcr p15,0,R0,c8,c7,0 ;Invalidate TLB
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mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array
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dsb
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isb
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bx LR
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ArmEnableDataCache
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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orr R0,R0,R1 ;Set C bit
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mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
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dsb
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isb
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bx LR
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ArmDisableDataCache
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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bic R0,R0,R1 ;Clear C bit
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mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
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isb
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bx LR
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ArmEnableInstructionCache
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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orr R0,R0,R1 ;Set I bit
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mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
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dsb
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isb
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bx LR
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ArmDisableInstructionCache
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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BIC R0,R0,R1 ;Clear I bit.
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mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
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isb
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bx LR
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ArmEnableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx LR
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ArmDisableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx LR
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ArmV7AllDataCachesOperation
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 ; Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
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ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
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mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
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beq Finished
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mov R10, #0
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Loop1
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add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
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mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
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and R12, R12, #7 ; get those 3 bits alone
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cmp R12, #2
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blt Skip ; no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb ; isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
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and R2, R12, #&7 ; extract the line length field
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add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
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ldr R4, =0x3FF
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ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
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clz R5, R4 ; R5 is the bit position of the way size increment
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ldr R7, =0x00007FFF
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ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
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Loop2
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mov R9, R4 ; R9 working copy of the max way size (right aligned)
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Loop3
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orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
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orr R0, R0, R7, LSL R2 ; factor in the index number
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blx R1
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subs R9, R9, #1 ; decrement the way number
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bge Loop3
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subs R7, R7, #1 ; decrement the index
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bge Loop2
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Skip
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add R10, R10, #2 ; increment the cache number
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cmp R3, R10
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bgt Loop1
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Finished
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dsb
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ldmfd SP!, {r4-r12, lr}
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bx LR
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ArmDataMemoryBarrier
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dmb
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bx LR
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ArmDataSyncronizationBarrier
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ArmDrainWriteBuffer
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dsb
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bx LR
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ArmInstructionSynchronizationBarrier
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isb
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bx LR
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END
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