mirror of https://github.com/acidanthera/audk.git
107 lines
3.1 KiB
ArmAsm
107 lines
3.1 KiB
ArmAsm
//++
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// Copyright (c) 2006, Intel Corporation
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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// Module Name:
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//
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// Cpu.s
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//
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// Abstract:
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//
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//
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// Revision History:
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//
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//--
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.file "Cpu.s"
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.radix D
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.section .text, "ax", "progbits"
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.align 32
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.section .pdata, "a", "progbits"
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.align 4
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.section .xdata, "a", "progbits"
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.align 8
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.section .data, "wa", "progbits"
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.align 16
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.section .rdata, "a", "progbits"
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.align 16
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.section .bss, "wa", "nobits"
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.align 16
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.section .tls$, "was", "progbits"
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.align 16
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.section .sdata, "was", "progbits"
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.align 16
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.section .sbss, "was", "nobits"
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.align 16
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.section .srdata, "as", "progbits"
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.align 16
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.section .rdata, "a", "progbits"
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.align 16
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.section .rtcode, "ax", "progbits"
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.align 32
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.type InvalidateInstructionCacheRange# ,@function
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.global InvalidateInstructionCacheRange#
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// Function compile flags: /Ogsy
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.section .rtcode
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// Begin code for function: InvalidateInstructionCacheRange:
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.proc InvalidateInstructionCacheRange#
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.align 32
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InvalidateInstructionCacheRange:
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// File e:\tmp\pioflush.c
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{ .mii //R-Addr: 0X00
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alloc r3=2, 0, 0, 0 //11, 00000002H
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cmp4.leu p0,p6=32, r33;; //15, 00000020H
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(p6) mov r33=32;; //16, 00000020H
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}
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{ .mii //R-Addr: 0X010
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nop.m 0
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zxt4 r29=r33;; //21
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dep.z r30=r29, 0, 5;; //21, 00000005H
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}
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{ .mii //R-Addr: 0X020
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cmp4.eq p0,p7=r0, r30 //21
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shr.u r28=r29, 5;; //19, 00000005H
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(p7) adds r28=1, r28;; //22, 00000001H
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}
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{ .mii //R-Addr: 0X030
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nop.m 0
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shl r27=r28, 5;; //25, 00000005H
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zxt4 r26=r27;; //25
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}
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{ .mfb //R-Addr: 0X040
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add r31=r26, r32 //25
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nop.f 0
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nop.b 0
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}
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$L143:
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{ .mii //R-Addr: 0X050
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fc r32 //27
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adds r32=32, r32;; //28, 00000020H
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cmp.ltu p14,p15=r32, r31 //29
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}
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{ .mfb //R-Addr: 0X060
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nop.m 0
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nop.f 0
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(p14) br.cond.dptk.few $L143#;; //29, 880000/120000
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}
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{ .mmi
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sync.i;;
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srlz.i
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nop.i 0;;
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}
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{ .mfb //R-Addr: 0X070
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nop.m 0
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nop.f 0
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br.ret.sptk.few b0;; //31
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}
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// End code for function:
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.endp InvalidateInstructionCacheRange#
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// END
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