mirror of https://github.com/acidanthera/audk.git
492 lines
14 KiB
C
492 lines
14 KiB
C
/** @file
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Code for Processor S3 restoration
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PiSmmCpuDxeSmm.h"
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typedef struct {
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UINTN Lock;
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VOID *StackStart;
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UINTN StackSize;
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VOID *ApFunction;
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IA32_DESCRIPTOR GdtrProfile;
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IA32_DESCRIPTOR IdtrProfile;
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UINT32 BufferStart;
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UINT32 Cr3;
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} MP_CPU_EXCHANGE_INFO;
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typedef struct {
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UINT8 *RendezvousFunnelAddress;
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UINTN PModeEntryOffset;
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UINTN FlatJumpOffset;
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UINTN Size;
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UINTN LModeEntryOffset;
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UINTN LongJumpOffset;
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} MP_ASSEMBLY_ADDRESS_MAP;
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/**
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Get starting address and size of the rendezvous entry for APs.
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Information for fixing a jump instruction in the code is also returned.
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@param AddressMap Output buffer for address map information.
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**/
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VOID *
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EFIAPI
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AsmGetAddressMap (
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MP_ASSEMBLY_ADDRESS_MAP *AddressMap
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);
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#define LEGACY_REGION_SIZE (2 * 0x1000)
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#define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
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#define MSR_SPIN_LOCK_INIT_NUM 15
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ACPI_CPU_DATA mAcpiCpuData;
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UINT32 mNumberToFinish;
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MP_CPU_EXCHANGE_INFO *mExchangeInfo;
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BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
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VOID *mGdtForAp = NULL;
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VOID *mIdtForAp = NULL;
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VOID *mMachineCheckHandlerForAp = NULL;
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MP_MSR_LOCK *mMsrSpinLocks = NULL;
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UINTN mMsrSpinLockCount = MSR_SPIN_LOCK_INIT_NUM;
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UINTN mMsrCount = 0;
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/**
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Get MSR spin lock by MSR index.
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@param MsrIndex MSR index value.
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@return Pointer to MSR spin lock.
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**/
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SPIN_LOCK *
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GetMsrSpinLockByIndex (
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IN UINT32 MsrIndex
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)
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{
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UINTN Index;
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for (Index = 0; Index < mMsrCount; Index++) {
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if (MsrIndex == mMsrSpinLocks[Index].MsrIndex) {
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return &mMsrSpinLocks[Index].SpinLock;
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}
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}
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return NULL;
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}
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/**
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Initialize MSR spin lock by MSR index.
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@param MsrIndex MSR index value.
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**/
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VOID
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InitMsrSpinLockByIndex (
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IN UINT32 MsrIndex
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)
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{
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UINTN NewMsrSpinLockCount;
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if (mMsrSpinLocks == NULL) {
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mMsrSpinLocks = (MP_MSR_LOCK *) AllocatePool (sizeof (MP_MSR_LOCK) * mMsrSpinLockCount);
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ASSERT (mMsrSpinLocks != NULL);
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}
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if (GetMsrSpinLockByIndex (MsrIndex) == NULL) {
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//
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// Initialize spin lock for MSR programming
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//
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mMsrSpinLocks[mMsrCount].MsrIndex = MsrIndex;
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InitializeSpinLock (&mMsrSpinLocks[mMsrCount].SpinLock);
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mMsrCount ++;
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if (mMsrCount == mMsrSpinLockCount) {
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//
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// If MSR spin lock buffer is full, enlarge it
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//
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NewMsrSpinLockCount = mMsrSpinLockCount + MSR_SPIN_LOCK_INIT_NUM;
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mMsrSpinLocks = ReallocatePool (
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sizeof (MP_MSR_LOCK) * mMsrSpinLockCount,
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sizeof (MP_MSR_LOCK) * NewMsrSpinLockCount,
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mMsrSpinLocks
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);
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mMsrSpinLockCount = NewMsrSpinLockCount;
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}
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}
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}
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/**
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Sync up the MTRR values for all processors.
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@param MtrrTable Table holding fixed/variable MTRR values to be loaded.
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**/
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VOID
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EFIAPI
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LoadMtrrData (
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EFI_PHYSICAL_ADDRESS MtrrTable
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)
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/*++
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Routine Description:
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Sync up the MTRR values for all processors.
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Arguments:
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Returns:
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None
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--*/
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{
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MTRR_SETTINGS *MtrrSettings;
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MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;
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MtrrSetAllMtrrs (MtrrSettings);
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}
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/**
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Programs registers for the calling processor.
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This function programs registers for the calling processor.
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@param RegisterTable Pointer to register table of the running processor.
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**/
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VOID
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SetProcessorRegister (
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IN CPU_REGISTER_TABLE *RegisterTable
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)
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{
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CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
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UINTN Index;
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UINTN Value;
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SPIN_LOCK *MsrSpinLock;
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//
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// Traverse Register Table of this logical processor
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//
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RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
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for (Index = 0; Index < RegisterTable->TableLength; Index++, RegisterTableEntry++) {
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//
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// Check the type of specified register
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//
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switch (RegisterTableEntry->RegisterType) {
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//
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// The specified register is Control Register
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//
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case ControlRegister:
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switch (RegisterTableEntry->Index) {
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case 0:
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Value = AsmReadCr0 ();
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Value = (UINTN) BitFieldWrite64 (
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Value,
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RegisterTableEntry->ValidBitStart,
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RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
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(UINTN) RegisterTableEntry->Value
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);
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AsmWriteCr0 (Value);
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break;
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case 2:
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Value = AsmReadCr2 ();
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Value = (UINTN) BitFieldWrite64 (
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Value,
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RegisterTableEntry->ValidBitStart,
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RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
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(UINTN) RegisterTableEntry->Value
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);
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AsmWriteCr2 (Value);
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break;
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case 3:
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Value = AsmReadCr3 ();
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Value = (UINTN) BitFieldWrite64 (
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Value,
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RegisterTableEntry->ValidBitStart,
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RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
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(UINTN) RegisterTableEntry->Value
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);
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AsmWriteCr3 (Value);
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break;
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case 4:
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Value = AsmReadCr4 ();
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Value = (UINTN) BitFieldWrite64 (
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Value,
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RegisterTableEntry->ValidBitStart,
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RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
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(UINTN) RegisterTableEntry->Value
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);
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AsmWriteCr4 (Value);
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break;
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default:
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break;
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}
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break;
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//
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// The specified register is Model Specific Register
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//
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case Msr:
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//
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// If this function is called to restore register setting after INIT signal,
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// there is no need to restore MSRs in register table.
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//
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if (RegisterTableEntry->ValidBitLength >= 64) {
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//
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// If length is not less than 64 bits, then directly write without reading
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//
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AsmWriteMsr64 (
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RegisterTableEntry->Index,
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RegisterTableEntry->Value
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);
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} else {
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//
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// Get lock to avoid Package/Core scope MSRs programming issue in parallel execution mode
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// to make sure MSR read/write operation is atomic.
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//
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MsrSpinLock = GetMsrSpinLockByIndex (RegisterTableEntry->Index);
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AcquireSpinLock (MsrSpinLock);
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//
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// Set the bit section according to bit start and length
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//
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AsmMsrBitFieldWrite64 (
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RegisterTableEntry->Index,
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RegisterTableEntry->ValidBitStart,
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RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
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RegisterTableEntry->Value
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);
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ReleaseSpinLock (MsrSpinLock);
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}
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break;
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//
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// Enable or disable cache
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//
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case CacheControl:
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//
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// If value of the entry is 0, then disable cache. Otherwise, enable cache.
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//
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if (RegisterTableEntry->Value == 0) {
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AsmDisableCache ();
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} else {
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AsmEnableCache ();
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}
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break;
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default:
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break;
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}
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}
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}
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/**
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AP initialization before SMBASE relocation in the S3 boot path.
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**/
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VOID
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EarlyMPRendezvousProcedure (
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VOID
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)
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{
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CPU_REGISTER_TABLE *RegisterTableList;
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UINT32 InitApicId;
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UINTN Index;
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LoadMtrrData (mAcpiCpuData.MtrrTable);
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//
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// Find processor number for this CPU.
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//
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RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable;
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InitApicId = GetInitialApicId ();
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for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
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if (RegisterTableList[Index].InitialApicId == InitApicId) {
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SetProcessorRegister (&RegisterTableList[Index]);
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break;
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}
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}
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//
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// Count down the number with lock mechanism.
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//
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InterlockedDecrement (&mNumberToFinish);
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}
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/**
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AP initialization after SMBASE relocation in the S3 boot path.
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**/
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VOID
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MPRendezvousProcedure (
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VOID
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)
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{
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CPU_REGISTER_TABLE *RegisterTableList;
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UINT32 InitApicId;
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UINTN Index;
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ProgramVirtualWireMode ();
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DisableLvtInterrupts ();
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RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable;
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InitApicId = GetInitialApicId ();
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for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
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if (RegisterTableList[Index].InitialApicId == InitApicId) {
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SetProcessorRegister (&RegisterTableList[Index]);
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break;
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}
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}
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//
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// Count down the number with lock mechanism.
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//
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InterlockedDecrement (&mNumberToFinish);
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}
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/**
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Prepares startup vector for APs.
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This function prepares startup vector for APs.
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@param WorkingBuffer The address of the work buffer.
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**/
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VOID
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PrepareApStartupVector (
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EFI_PHYSICAL_ADDRESS WorkingBuffer
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)
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{
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EFI_PHYSICAL_ADDRESS StartupVector;
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MP_ASSEMBLY_ADDRESS_MAP AddressMap;
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//
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// Get the address map of startup code for AP,
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// including code size, and offset of long jump instructions to redirect.
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//
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ZeroMem (&AddressMap, sizeof (AddressMap));
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AsmGetAddressMap (&AddressMap);
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StartupVector = WorkingBuffer;
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//
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// Copy AP startup code to startup vector, and then redirect the long jump
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// instructions for mode switching.
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//
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CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
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*(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);
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if (AddressMap.LongJumpOffset != 0) {
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*(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);
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}
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//
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// Get the start address of exchange data between BSP and AP.
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//
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mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);
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ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
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CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
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CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
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//
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// Copy AP's GDT, IDT and Machine Check handler from SMRAM to ACPI NVS memory
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//
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CopyMem ((VOID *) mExchangeInfo->GdtrProfile.Base, mGdtForAp, mExchangeInfo->GdtrProfile.Limit + 1);
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CopyMem ((VOID *) mExchangeInfo->IdtrProfile.Base, mIdtForAp, mExchangeInfo->IdtrProfile.Limit + 1);
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CopyMem ((VOID *)(UINTN) mAcpiCpuData.ApMachineCheckHandlerBase, mMachineCheckHandlerForAp, mAcpiCpuData.ApMachineCheckHandlerSize);
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mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
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mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
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mExchangeInfo->BufferStart = (UINT32) StartupVector;
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mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
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}
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/**
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The function is invoked before SMBASE relocation in S3 path to restores CPU status.
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The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
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and restores MTRRs for both BSP and APs.
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**/
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VOID
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EarlyInitializeCpu (
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VOID
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)
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{
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CPU_REGISTER_TABLE *RegisterTableList;
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UINT32 InitApicId;
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UINTN Index;
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LoadMtrrData (mAcpiCpuData.MtrrTable);
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//
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// Find processor number for this CPU.
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//
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RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable;
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InitApicId = GetInitialApicId ();
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for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
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if (RegisterTableList[Index].InitialApicId == InitApicId) {
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SetProcessorRegister (&RegisterTableList[Index]);
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break;
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}
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}
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ProgramVirtualWireMode ();
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PrepareApStartupVector (mAcpiCpuData.StartupVector);
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mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
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mExchangeInfo->ApFunction = (VOID *) (UINTN) EarlyMPRendezvousProcedure;
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//
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// Send INIT IPI - SIPI to all APs
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//
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SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
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while (mNumberToFinish > 0) {
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CpuPause ();
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}
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}
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/**
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The function is invoked after SMBASE relocation in S3 path to restores CPU status.
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The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
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data saved by normal boot path for both BSP and APs.
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**/
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VOID
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InitializeCpu (
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VOID
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)
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{
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CPU_REGISTER_TABLE *RegisterTableList;
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UINT32 InitApicId;
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UINTN Index;
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RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable;
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InitApicId = GetInitialApicId ();
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for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
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if (RegisterTableList[Index].InitialApicId == InitApicId) {
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SetProcessorRegister (&RegisterTableList[Index]);
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break;
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}
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}
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mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
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//
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// StackStart was updated when APs were waken up in EarlyInitializeCpu.
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// Re-initialize StackAddress to original beginning address.
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//
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mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
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mExchangeInfo->ApFunction = (VOID *) (UINTN) MPRendezvousProcedure;
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//
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// Send INIT IPI - SIPI to all APs
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//
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SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
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while (mNumberToFinish > 0) {
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CpuPause ();
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}
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}
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