mirror of https://github.com/acidanthera/audk.git
964 lines
32 KiB
C
964 lines
32 KiB
C
/** @file
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The header file provides interface definitions exposed by CSM (Compatible Support Module).
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The CSM provides compatibility support between the Framework and traditional, legacy BIOS code
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and allows booting a traditional OS or booting an EFI OS off a device that requires a traditional
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option ROM (OpROM).
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These definitions are from Compatibility Support Module Spec Version 0.97.
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Copyright (c) 2007-2009, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Revision Reference:
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These definitions are from Compatibility Support Module Spec
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Version 0.97.
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**/
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#ifndef _FRAMEWORK_LEGACY_16_H_
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#define _FRAMEWORK_LEGACY_16_H_
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#pragma pack(1)
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typedef UINT8 SERIAL_MODE;
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typedef UINT8 PARALLEL_MODE;
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#define EFI_COMPATIBILITY16_TABLE_SIGNATURE SIGNATURE_32 ('I', 'F', 'E', '$')
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///
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/// There is a table located within the traditional BIOS in either the 0xF000:xxxx or 0xE000:xxxx
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/// physical address range. It is located on a 16-byte boundary and provides the physical address of the
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/// entry point for the Compatibility16 functions. These functions provide the platform-specific
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/// information that is required by the generic EfiCompatibility code. The functions are invoked via
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/// thunking by using EFI_LEGACY_BIOS_PROTOCOL.FarCall86() with the 32-bit physical
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/// entry point.
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///
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typedef struct {
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///
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/// The string "$EFI" denotes the start of the EfiCompatibility table. Byte 0 is "I," byte
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/// 1 is "F," byte 2 is "E," and byte 3 is "$" and is normally accessed as a DWORD or UINT32.
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///
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UINT32 Signature;
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///
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/// The value required such that byte checksum of TableLength equals zero.
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///
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UINT8 TableChecksum;
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///
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/// The length of this table.
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///
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UINT8 TableLength;
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///
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/// The major EFI revision for which this table was generated.
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///
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UINT8 EfiMajorRevision;
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///
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/// The minor EFI revision for which this table was generated.
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///
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UINT8 EfiMinorRevision;
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///
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/// The major revision of this table.
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///
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UINT8 TableMajorRevision;
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///
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/// The minor revision of this table.
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///
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UINT8 TableMinorRevision;
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///
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/// Reserved for future usage.
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///
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UINT16 Reserved;
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///
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/// The segment of the entry point within the traditional BIOS for Compatibility16 functions.
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///
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UINT16 Compatibility16CallSegment;
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///
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/// The offset of the entry point within the traditional BIOS for Compatibility16 functions.
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///
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UINT16 Compatibility16CallOffset;
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///
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/// The segment of the entry point within the traditional BIOS for EfiCompatibility to invoke the PnP installation check.
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///
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UINT16 PnPInstallationCheckSegment;
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///
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/// The Offset of the entry point within the traditional BIOS for EfiCompatibility to invoke the PnP installation check.
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///
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UINT16 PnPInstallationCheckOffset;
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///
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/// EFI system resources table. Type EFI_SYSTEM_TABLE is defined in the IntelPlatform Innovation Framework for EFI
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/// Driver Execution Environment Core Interface Specification (DXE CIS).
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///
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UINT32 EfiSystemTable;
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///
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/// The address of an OEM-provided identifier string. The string is null terminated.
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///
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UINT32 OemIdStringPointer;
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///
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/// The 32-bit physical address where ACPI RSD PTR is stored within the traditional
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/// BIOS. The remained of the ACPI tables are located at their EFI addresses. The size
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/// reserved is the maximum for ACPI 2.0. The EfiCompatibility will fill in the ACPI
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/// RSD PTR with either the ACPI 1.0b or 2.0 values.
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///
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UINT32 AcpiRsdPtrPointer;
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///
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/// The OEM revision number. Usage is undefined but provided for OEM module usage.
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///
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UINT16 OemRevision;
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///
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/// The 32-bit physical address where INT15 E820 data is stored within the traditional
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/// BIOS. The EfiCompatibility code will fill in the E820Pointer value and copy the
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/// data to the indicated area.
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///
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UINT32 E820Pointer;
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///
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/// The length of the E820 data and is filled in by the EfiCompatibility code.
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///
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UINT32 E820Length;
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///
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/// The 32-bit physical address where the $PIR table is stored in the traditional BIOS.
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/// The EfiCompatibility code will fill in the IrqRoutingTablePointer value and
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/// copy the data to the indicated area.
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///
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UINT32 IrqRoutingTablePointer;
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///
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/// The length of the $PIR table and is filled in by the EfiCompatibility code.
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///
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UINT32 IrqRoutingTableLength;
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///
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/// The 32-bit physical address where the MP table is stored in the traditional BIOS.
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/// The EfiCompatibility code will fill in the MpTablePtr value and copy the data to the indicated area.
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///
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UINT32 MpTablePtr;
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///
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/// The length of the MP table and is filled in by the EfiCompatibility code.
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///
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UINT32 MpTableLength;
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///
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/// The segment of the OEM-specific INT table/code.
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///
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UINT16 OemIntSegment;
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///
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/// The offset of the OEM-specific INT table/code.
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///
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UINT16 OemIntOffset;
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///
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/// The segment of the OEM-specific 32-bit table/code.
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///
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UINT16 Oem32Segment;
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///
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/// The offset of the OEM-specific 32-bit table/code.
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///
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UINT16 Oem32Offset;
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///
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/// The segment of the OEM-specific 16-bit table/code.
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///
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UINT16 Oem16Segment;
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///
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/// The offset of the OEM-specific 16-bit table/code.
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///
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UINT16 Oem16Offset;
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///
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/// The segment of the TPM binary passed to 16-bit CSM.
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///
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UINT16 TpmSegment;
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///
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/// The offset of the TPM binary passed to 16-bit CSM.
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///
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UINT16 TpmOffset;
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///
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/// A pointer to a string identifying the independent BIOS vendor.
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///
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UINT32 IbvPointer;
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///
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/// This field is NULL for all systems not supporting PCI Express. This field is the base
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/// value of the start of the PCI Express memory-mapped configuration registers and
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/// must be filled in prior to EfiCompatibility code issuing the Compatibility16 function
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/// Compatibility16InitializeYourself().
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/// Compatibility16InitializeYourself() is defined in Compatability16
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/// Functions.
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///
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UINT32 PciExpressBase;
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///
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/// Maximum PCI bus number assigned.
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///
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UINT8 LastPciBus;
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} EFI_COMPATIBILITY16_TABLE;
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///
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/// Functions provided by the CSM binary which communicate between the EfiCompatibility
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/// and Compatability16 code.
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///
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/// Inconsistent with specification here:
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/// The member's name started with "Compatibility16" [defined in Intel Framework Compatibility Support Module Specification / 0.97 version]
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/// has been changed to "Legacy16" since keeping backward compatible.
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///
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typedef enum {
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///
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/// Causes the Compatibility16 code to do any internal initialization required.
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/// Input:
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/// AX = Compatibility16InitializeYourself
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/// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_INIT_TABLE
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/// Return:
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/// AX = Return Status codes
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///
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Legacy16InitializeYourself = 0x0000,
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///
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/// Causes the Compatibility16 BIOS to perform any drive number translations to match the boot sequence.
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/// Input:
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/// AX = Compatibility16UpdateBbs
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/// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE
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/// Return:
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/// AX = Returned status codes
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///
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Legacy16UpdateBbs = 0x0001,
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///
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/// Allows the Compatibility16 code to perform any final actions before booting. The Compatibility16
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/// code is read/write.
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/// Input:
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/// AX = Compatibility16PrepareToBoot
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/// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE structure
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/// Return:
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/// AX = Returned status codes
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///
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Legacy16PrepareToBoot = 0x0002,
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///
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/// Causes the Compatibility16 BIOS to boot. The Compatibility16 code is Read/Only.
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/// Input:
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/// AX = Compatibility16Boot
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/// Output:
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/// AX = Returned status codes
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///
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Legacy16Boot = 0x0003,
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///
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/// Allows the Compatibility16 code to get the last device from which a boot was attempted. This is
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/// stored in CMOS and is the priority number of the last attempted boot device.
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/// Input:
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/// AX = Compatibility16RetrieveLastBootDevice
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/// Output:
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/// AX = Returned status codes
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/// BX = Priority number of the boot device.
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///
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Legacy16RetrieveLastBootDevice = 0x0004,
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///
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/// Allows the Compatibility16 code rehook INT13, INT18, and/or INT19 after dispatching a legacy OpROM.
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/// Input:
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/// AX = Compatibility16DispatchOprom
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/// ES:BX = Pointer to EFI_DISPATCH_OPROM_TABLE
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/// Output:
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/// AX = Returned status codes
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/// BX = Number of non-BBS-compliant devices found. Equals 0 if BBS compliant.
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///
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Legacy16DispatchOprom = 0x0005,
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///
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/// Finds a free area in the 0xFxxxx or 0xExxxx region of the specified length and returns the address
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/// of that region.
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/// Input:
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/// AX = Compatibility16GetTableAddress
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/// BX = Allocation region
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/// 00 = Allocate from either 0xE0000 or 0xF0000 64 KB blocks.
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/// Bit 0 = 1 Allocate from 0xF0000 64 KB block
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/// Bit 1 = 1 Allocate from 0xE0000 64 KB block
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/// CX = Requested length in bytes.
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/// DX = Required address alignment. Bit mapped. First non-zero bit from the right is the alignment.
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/// Output:
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/// AX = Returned status codes
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/// DS:BX = Address of the region
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///
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Legacy16GetTableAddress = 0x0006,
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///
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/// Enables the EfiCompatibility module to do any nonstandard processing of keyboard LEDs or state.
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/// Input:
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/// AX = Compatibility16SetKeyboardLeds
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/// CL = LED status.
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/// Bit 0 Scroll Lock 0 = Off
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/// Bit 1 NumLock
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/// Bit 2 Caps Lock
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/// Output:
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/// AX = Returned status codes
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///
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Legacy16SetKeyboardLeds = 0x0007,
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///
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/// Enables the EfiCompatibility module to install an interrupt handler for PCI mass media devices that
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/// do not have an OpROM associated with them. An example is SATA.
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/// Input:
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/// AX = Compatibility16InstallPciHandler
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/// ES:BX = Pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure
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/// Output:
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/// AX = Returned status codes
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///
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Legacy16InstallPciHandler = 0x0008
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} EFI_COMPATIBILITY_FUNCTIONS;
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///
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/// EFI_DISPATCH_OPROM_TABLE
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///
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typedef struct {
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UINT16 PnPInstallationCheckSegment; ///< Pointer to the PnpInstallationCheck data structure.
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UINT16 PnPInstallationCheckOffset; ///< Pointer to the PnpInstallationCheck data structure.
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UINT16 OpromSegment; ///< The segment where the OpROM was placed. Offset is assumed to be 3.
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UINT8 PciBus; ///< The PCI bus.
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UINT8 PciDeviceFunction; ///< The PCI device * 0x08 | PCI function.
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UINT8 NumberBbsEntries; ///< The number of valid BBS table entries upon entry and exit. The IBV code may
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///< increase this number, if BBS-compliant devices also hook INTs in order to force the
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///< OpROM BIOS Setup to be executed.
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VOID *BbsTablePointer; ///< Pointer to the BBS table.
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UINT16 RuntimeSegment; ///< The segment where the OpROM can be relocated to. If this value is 0x0000, this
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///< means that the relocation of this run time code is not supported.
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///< Inconsistent with specification here:
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///< The member's name "OpromDestinationSegment" [defined in Intel Framework Compatibility Support Module Specification / 0.97 version]
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///< has been changed to "RuntimeSegment" since keeping backward compatible.
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} EFI_DISPATCH_OPROM_TABLE;
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///
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/// EFI_TO_COMPATIBILITY16_INIT_TABLE
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///
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typedef struct {
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///
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/// Starting address of memory under 1 MB. The ending address is assumed to be 640 KB or 0x9FFFF.
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///
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UINT32 BiosLessThan1MB;
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///
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/// Starting address of the high memory block.
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///
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UINT32 HiPmmMemory;
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///
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/// Length of high memory block.
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///
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UINT32 HiPmmMemorySizeInBytes;
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///
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/// The segment of the reverse thunk call code.
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///
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UINT16 ReverseThunkCallSegment;
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///
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/// The offset of the reverse thunk call code.
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///
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UINT16 ReverseThunkCallOffset;
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///
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/// The number of E820 entries copied to the Compatibility16 BIOS.
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///
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UINT32 NumberE820Entries;
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///
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/// The amount of usable memory above 1 MB, e.g., E820 type 1 memory.
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///
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UINT32 OsMemoryAbove1Mb;
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///
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/// The start of thunk code in main memory. Memory cannot be used by BIOS or PMM.
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///
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UINT32 ThunkStart;
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///
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/// The size of the thunk code.
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///
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UINT32 ThunkSizeInBytes;
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///
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/// Starting address of memory under 1 MB.
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///
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UINT32 LowPmmMemory;
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///
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/// Length of low Memory block.
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///
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UINT32 LowPmmMemorySizeInBytes;
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} EFI_TO_COMPATIBILITY16_INIT_TABLE;
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///
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/// DEVICE_PRODUCER_SERIAL
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///
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typedef struct {
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UINT16 Address; ///< I/O address assigned to the serial port
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UINT8 Irq; ///< IRQ assigned to the serial port.
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SERIAL_MODE Mode; ///< Mode of serial port. Values are defined below.
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} DEVICE_PRODUCER_SERIAL;
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///
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/// DEVICE_PRODUCER_SERIAL's modes
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///@{
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#define DEVICE_SERIAL_MODE_NORMAL 0x00
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#define DEVICE_SERIAL_MODE_IRDA 0x01
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#define DEVICE_SERIAL_MODE_ASK_IR 0x02
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#define DEVICE_SERIAL_MODE_DUPLEX_HALF 0x00
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#define DEVICE_SERIAL_MODE_DUPLEX_FULL 0x10
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///@)
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///
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/// DEVICE_PRODUCER_PARALLEL
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///
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typedef struct {
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UINT16 Address; ///< I/O address assigned to the parallel port
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UINT8 Irq; ///< IRQ assigned to the parallel port.
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UINT8 Dma; ///< DMA assigned to the parallel port.
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PARALLEL_MODE Mode; ///< Mode of the parallel port. Values are defined below.
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} DEVICE_PRODUCER_PARALLEL;
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///
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/// DEVICE_PRODUCER_PARALLEL's modes
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///@{
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#define DEVICE_PARALLEL_MODE_MODE_OUTPUT_ONLY 0x00
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#define DEVICE_PARALLEL_MODE_MODE_BIDIRECTIONAL 0x01
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#define DEVICE_PARALLEL_MODE_MODE_EPP 0x02
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#define DEVICE_PARALLEL_MODE_MODE_ECP 0x03
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///@}
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///
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/// DEVICE_PRODUCER_FLOPPY
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///
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typedef struct {
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UINT16 Address; ///< I/O address assigned to the floppy
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UINT8 Irq; ///< IRQ assigned to the floppy.
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UINT8 Dma; ///< DMA assigned to the floppy.
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UINT8 NumberOfFloppy; ///< Number of floppies in the system.
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} DEVICE_PRODUCER_FLOPPY;
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///
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/// LEGACY_DEVICE_FLAGS
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///
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typedef struct {
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UINT32 A20Kybd : 1; ///< A20 controller by keyboard controller.
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UINT32 A20Port90 : 1; ///< A20 controlled by port 0x92.
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UINT32 Reserved : 30; ///< Reserved for future usage.
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} LEGACY_DEVICE_FLAGS;
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///
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/// DEVICE_PRODUCER_DATA_HEADER
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///
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typedef struct {
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DEVICE_PRODUCER_SERIAL Serial[4]; ///< Data for serial port x. Type DEVICE_PRODUCER_SERIAL is defined below.
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DEVICE_PRODUCER_PARALLEL Parallel[3]; ///< Data for parallel port x. Type DEVICE_PRODUCER_PARALLEL is defined below.
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DEVICE_PRODUCER_FLOPPY Floppy; ///< Data for floppy. Type DEVICE_PRODUCER_FLOPPY is defined below.
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UINT8 MousePresent; ///< Flag to indicate if mouse is present.
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LEGACY_DEVICE_FLAGS Flags; ///< Miscellaneous Boolean state information passed to CSM.
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} DEVICE_PRODUCER_DATA_HEADER;
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///
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/// ATAPI_IDENTIFY
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///
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typedef struct {
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UINT16 Raw[256]; ///< Raw data from the IDE IdentifyDrive command.
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} ATAPI_IDENTIFY;
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///
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/// HDD_INFO
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///
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typedef struct {
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///
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/// Status of IDE device. Values are defined below. There is one HDD_INFO structure
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/// per IDE controller. The IdentifyDrive is per drive. Index 0 is master and index
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/// 1 is slave.
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///
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UINT16 Status;
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///
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/// PCI bus of IDE controller.
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///
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UINT32 Bus;
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///
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/// PCI device of IDE controller.
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///
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UINT32 Device;
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///
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/// PCI function of IDE controller.
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///
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UINT32 Function;
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///
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/// Command ports base address.
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///
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UINT16 CommandBaseAddress;
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///
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/// Control ports base address.
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///
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UINT16 ControlBaseAddress;
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///
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/// Bus master address
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///
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UINT16 BusMasterAddress;
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UINT8 HddIrq;
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///
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/// Data that identifies the drive data, one per possible attached drive
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///
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ATAPI_IDENTIFY IdentifyDrive[2];
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} HDD_INFO;
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///
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/// HDD_INFO status bits
|
|
///
|
|
#define HDD_PRIMARY 0x01
|
|
#define HDD_SECONDARY 0x02
|
|
#define HDD_MASTER_ATAPI_CDROM 0x04
|
|
#define HDD_SLAVE_ATAPI_CDROM 0x08
|
|
#define HDD_MASTER_IDE 0x20
|
|
#define HDD_SLAVE_IDE 0x40
|
|
#define HDD_MASTER_ATAPI_ZIPDISK 0x10
|
|
#define HDD_SLAVE_ATAPI_ZIPDISK 0x80
|
|
|
|
///
|
|
/// BBS_STATUS_FLAGS
|
|
///
|
|
typedef struct {
|
|
UINT16 OldPosition : 4; ///< Prior priority.
|
|
UINT16 Reserved1 : 4; ///< Reserved for future use.
|
|
UINT16 Enabled : 1; ///< If 0, ignore this entry.
|
|
UINT16 Failed : 1; ///< 0 = Not known if boot failure occurred.
|
|
///< 1 = Boot attempted failed.
|
|
|
|
///
|
|
/// State of media present.
|
|
/// 00 = No bootable media is present in the device.
|
|
/// 01 = Unknown if a bootable media present.
|
|
/// 10 = Media is present and appears bootable.
|
|
/// 11 = Reserved.
|
|
///
|
|
UINT16 MediaPresent : 2;
|
|
UINT16 Reserved2 : 4; ///< Reserved for future use.
|
|
} BBS_STATUS_FLAGS;
|
|
|
|
///
|
|
/// BBS_TABLE, device type values & boot priority values
|
|
///
|
|
typedef struct {
|
|
///
|
|
/// The boot priority for this boot device. Values are defined below.
|
|
///
|
|
UINT16 BootPriority;
|
|
|
|
///
|
|
/// The PCI bus for this boot device.
|
|
///
|
|
UINT32 Bus;
|
|
|
|
///
|
|
/// The PCI device for this boot device.
|
|
///
|
|
UINT32 Device;
|
|
|
|
///
|
|
/// The PCI function for the boot device.
|
|
///
|
|
UINT32 Function;
|
|
|
|
///
|
|
/// The PCI class for this boot device.
|
|
///
|
|
UINT8 Class;
|
|
|
|
///
|
|
/// The PCI Subclass for this boot device.
|
|
///
|
|
UINT8 SubClass;
|
|
|
|
///
|
|
/// Segment:offset address of an ASCIIZ description string describing the manufacturer.
|
|
///
|
|
UINT16 MfgStringOffset;
|
|
|
|
///
|
|
/// Segment:offset address of an ASCIIZ description string describing the manufacturer.
|
|
///
|
|
UINT16 MfgStringSegment;
|
|
|
|
///
|
|
/// BBS device type. BBS device types are defined below.
|
|
///
|
|
UINT16 DeviceType;
|
|
|
|
///
|
|
/// Status of this boot device. Type BBS_STATUS_FLAGS is defined below.
|
|
///
|
|
BBS_STATUS_FLAGS StatusFlags;
|
|
|
|
///
|
|
/// Segment:Offset address of boot loader for IPL devices or install INT13 handler for
|
|
/// BCV devices.
|
|
///
|
|
UINT16 BootHandlerOffset;
|
|
|
|
///
|
|
/// Segment:Offset address of boot loader for IPL devices or install INT13 handler for
|
|
/// BCV devices.
|
|
///
|
|
UINT16 BootHandlerSegment;
|
|
|
|
///
|
|
/// Segment:offset address of an ASCIIZ description string describing this device.
|
|
///
|
|
UINT16 DescStringOffset;
|
|
|
|
///
|
|
/// Segment:offset address of an ASCIIZ description string describing this device.
|
|
///
|
|
UINT16 DescStringSegment;
|
|
|
|
///
|
|
/// Reserved.
|
|
///
|
|
UINT32 InitPerReserved;
|
|
|
|
///
|
|
/// The use of these fields is IBV dependent. They can be used to flag that an OpROM
|
|
/// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI
|
|
/// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup
|
|
///
|
|
UINT32 AdditionalIrq13Handler;
|
|
|
|
///
|
|
/// The use of these fields is IBV dependent. They can be used to flag that an OpROM
|
|
/// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI
|
|
/// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup
|
|
///
|
|
UINT32 AdditionalIrq18Handler;
|
|
|
|
///
|
|
/// The use of these fields is IBV dependent. They can be used to flag that an OpROM
|
|
/// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI
|
|
/// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup
|
|
///
|
|
UINT32 AdditionalIrq19Handler;
|
|
|
|
///
|
|
/// The use of these fields is IBV dependent. They can be used to flag that an OpROM
|
|
/// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI
|
|
/// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup
|
|
///
|
|
UINT32 AdditionalIrq40Handler;
|
|
UINT8 AssignedDriveNumber;
|
|
UINT32 AdditionalIrq41Handler;
|
|
UINT32 AdditionalIrq46Handler;
|
|
UINT32 IBV1;
|
|
UINT32 IBV2;
|
|
} BBS_TABLE;
|
|
|
|
///
|
|
/// BBS device type values
|
|
///@{
|
|
#define BBS_FLOPPY 0x01
|
|
#define BBS_HARDDISK 0x02
|
|
#define BBS_CDROM 0x03
|
|
#define BBS_PCMCIA 0x04
|
|
#define BBS_USB 0x05
|
|
#define BBS_EMBED_NETWORK 0x06
|
|
#define BBS_BEV_DEVICE 0x80
|
|
#define BBS_UNKNOWN 0xff
|
|
///@}
|
|
|
|
///
|
|
/// BBS boot priority values
|
|
///@{
|
|
#define BBS_DO_NOT_BOOT_FROM 0xFFFC
|
|
#define BBS_LOWEST_PRIORITY 0xFFFD
|
|
#define BBS_UNPRIORITIZED_ENTRY 0xFFFE
|
|
#define BBS_IGNORE_ENTRY 0xFFFF
|
|
///@}
|
|
|
|
///
|
|
/// SMM_ATTRIBUTES
|
|
///
|
|
typedef struct {
|
|
///
|
|
/// Access mechanism used to generate the soft SMI. Defined types are below. The other
|
|
/// values are reserved for future usage.
|
|
///
|
|
UINT16 Type : 3;
|
|
|
|
///
|
|
/// Size of "port" in bits. Defined values are below.
|
|
///
|
|
UINT16 PortGranularity : 3;
|
|
|
|
///
|
|
/// Size of data in bits. Defined values are below.
|
|
///
|
|
UINT16 DataGranularity : 3;
|
|
|
|
///
|
|
/// Reserved for future use.
|
|
///
|
|
UINT16 Reserved : 7;
|
|
} SMM_ATTRIBUTES;
|
|
|
|
///
|
|
/// SMM_ATTRIBUTES type values
|
|
///@{
|
|
#define STANDARD_IO 0x00
|
|
#define STANDARD_MEMORY 0x01
|
|
///@}
|
|
|
|
///
|
|
/// SMM_ATTRIBUTES port size constants
|
|
///@{
|
|
#define PORT_SIZE_8 0x00
|
|
#define PORT_SIZE_16 0x01
|
|
#define PORT_SIZE_32 0x02
|
|
#define PORT_SIZE_64 0x03
|
|
///@}
|
|
|
|
///
|
|
/// SMM_ATTRIBUTES data size constants
|
|
///@{
|
|
#define DATA_SIZE_8 0x00
|
|
#define DATA_SIZE_16 0x01
|
|
#define DATA_SIZE_32 0x02
|
|
#define DATA_SIZE_64 0x03
|
|
///@}
|
|
|
|
///
|
|
/// SMM_FUNCTION & relating constants
|
|
///
|
|
typedef struct {
|
|
UINT16 Function : 15;
|
|
UINT16 Owner : 1;
|
|
} SMM_FUNCTION;
|
|
|
|
///
|
|
/// SMM_FUNCTION Function constants
|
|
///@{
|
|
#define INT15_D042 0x0000
|
|
#define GET_USB_BOOT_INFO 0x0001
|
|
#define DMI_PNP_50_57 0x0002
|
|
///@}
|
|
|
|
///
|
|
/// SMM_FUNCTION Owner constants
|
|
///@{
|
|
#define STANDARD_OWNER 0x0
|
|
#define OEM_OWNER 0x1
|
|
///@}
|
|
|
|
/**
|
|
* SMM_ENTRY
|
|
*
|
|
* This structure assumes both port and data sizes are 1. SmmAttribute must be
|
|
* properly to reflect that assumption.
|
|
**/
|
|
typedef struct {
|
|
///
|
|
/// Describes the access mechanism, SmmPort, and SmmData sizes. Type
|
|
/// SMM_ATTRIBUTES is defined below.
|
|
///
|
|
SMM_ATTRIBUTES SmmAttributes;
|
|
|
|
///
|
|
/// Function Soft SMI is to perform. Type SMM_FUNCTION is defined below.
|
|
///
|
|
SMM_FUNCTION SmmFunction;
|
|
|
|
///
|
|
/// SmmPort size depends upon SmmAttributes and ranges from2 bytes to 16 bytes
|
|
///
|
|
UINT8 SmmPort;
|
|
|
|
///
|
|
/// SmmData size depends upon SmmAttributes and ranges from2 bytes to 16 bytes
|
|
///
|
|
UINT8 SmmData;
|
|
} SMM_ENTRY;
|
|
|
|
///
|
|
/// SMM_TABLE
|
|
///
|
|
typedef struct {
|
|
UINT16 NumSmmEntries; ///< Number of entries represented by SmmEntry.
|
|
SMM_ENTRY SmmEntry; ///< One entry per function. Type SMM_ENTRY is defined below.
|
|
} SMM_TABLE;
|
|
|
|
///
|
|
/// UDC_ATTRIBUTES
|
|
///
|
|
typedef struct {
|
|
///
|
|
/// This bit set indicates that the ServiceAreaData is valid.
|
|
///
|
|
UINT8 DirectoryServiceValidity : 1;
|
|
|
|
///
|
|
/// This bit set indicates to use the Reserve Area Boot Code Address (RACBA) only if
|
|
/// DirectoryServiceValidity is 0.
|
|
///
|
|
UINT8 RabcaUsedFlag : 1;
|
|
|
|
///
|
|
/// This bit set indicates to execute hard disk diagnostics.
|
|
///
|
|
UINT8 ExecuteHddDiagnosticsFlag : 1;
|
|
|
|
///
|
|
/// Reserved for future use. Set to 0.
|
|
///
|
|
UINT8 Reserved : 5;
|
|
} UDC_ATTRIBUTES;
|
|
|
|
///
|
|
/// UD_TABLE
|
|
///
|
|
typedef struct {
|
|
///
|
|
/// This field contains the bit-mapped attributes of the PARTIES information. Type
|
|
/// UDC_ATTRIBUTES is defined below.
|
|
///
|
|
UDC_ATTRIBUTES Attributes;
|
|
|
|
///
|
|
/// This field contains the zero-based device on which the selected
|
|
/// ServiceDataArea is present. It is 0 for master and 1 for the slave device.
|
|
///
|
|
UINT8 DeviceNumber;
|
|
|
|
///
|
|
/// This field contains the zero-based index into the BbsTable for the parent device.
|
|
/// This index allows the user to reference the parent device information such as PCI
|
|
/// bus, device function.
|
|
///
|
|
UINT8 BbsTableEntryNumberForParentDevice;
|
|
|
|
///
|
|
/// This field contains the zero-based index into the BbsTable for the boot entry.
|
|
///
|
|
UINT8 BbsTableEntryNumberForBoot;
|
|
|
|
///
|
|
/// This field contains the zero-based index into the BbsTable for the HDD diagnostics entry.
|
|
///
|
|
UINT8 BbsTableEntryNumberForHddDiag;
|
|
|
|
///
|
|
/// The raw Beer data.
|
|
///
|
|
UINT8 BeerData[128];
|
|
|
|
///
|
|
/// The raw data of selected service area.
|
|
///
|
|
UINT8 ServiceAreaData[64];
|
|
} UD_TABLE;
|
|
|
|
#define EFI_TO_LEGACY_MAJOR_VERSION 0x02
|
|
#define EFI_TO_LEGACY_MINOR_VERSION 0x00
|
|
#define MAX_IDE_CONTROLLER 8
|
|
|
|
///
|
|
/// EFI_TO_COMPATIBILITY16_BOOT_TABLE
|
|
///
|
|
typedef struct {
|
|
UINT16 MajorVersion; ///< The EfiCompatibility major version number.
|
|
UINT16 MinorVersion; ///< The EfiCompatibility minor version number.
|
|
UINT32 AcpiTable; ///< Location of the RSDT ACPI table. < 4G range
|
|
UINT32 SmbiosTable; ///< Location of the SMBIOS table in EFI memory. < 4G range
|
|
UINT32 SmbiosTableLength;
|
|
//
|
|
// Legacy SIO state
|
|
//
|
|
DEVICE_PRODUCER_DATA_HEADER SioData; ///< Standard traditional device information.
|
|
UINT16 DevicePathType; ///< The default boot type.
|
|
UINT16 PciIrqMask; ///< Mask of which IRQs have been assigned to PCI.
|
|
UINT32 NumberE820Entries; ///< Number of E820 entries. The number can change from the
|
|
///< Compatibility16InitializeYourself() function.
|
|
//
|
|
// Controller & Drive Identify[2] per controller information
|
|
//
|
|
HDD_INFO HddInfo[MAX_IDE_CONTROLLER]; ///< Hard disk drive information, including raw Identify Drive data.
|
|
UINT32 NumberBbsEntries; ///< Number of entries in the BBS table
|
|
UINT32 BbsTable; ///< Pointer to the BBS table. Type BBS_TABLE is defined below.
|
|
UINT32 SmmTable; ///< Pointer to the SMM table. Type SMM_TABLE is defined below.
|
|
UINT32 OsMemoryAbove1Mb; ///< The amount of usable memory above 1 MB, i.e. E820 type 1 memory. This value can
|
|
///< differ from the value in EFI_TO_COMPATIBILITY16_INIT_TABLE as more
|
|
///< memory may have been discovered.
|
|
UINT32 UnconventionalDeviceTable; ///< Information to boot off an unconventional device like a PARTIES partition. Type
|
|
///< UD_TABLE is defined below.
|
|
} EFI_TO_COMPATIBILITY16_BOOT_TABLE;
|
|
|
|
///
|
|
/// EFI_LEGACY_INSTALL_PCI_HANDLER
|
|
///
|
|
typedef struct {
|
|
UINT8 PciBus; ///< The PCI bus of the device.
|
|
UINT8 PciDeviceFun; ///< The PCI device in bits 7:3 and function in bits 2:0.
|
|
UINT8 PciSegment; ///< The PCI segment of the device.
|
|
UINT8 PciClass; ///< The PCI class code of the device.
|
|
UINT8 PciSubclass; ///< The PCI subclass code of the device.
|
|
UINT8 PciInterface; ///< The PCI interface code of the device.
|
|
//
|
|
// Primary section
|
|
//
|
|
UINT8 PrimaryIrq; ///< The primary device IRQ.
|
|
UINT8 PrimaryReserved; ///< Reserved.
|
|
UINT16 PrimaryControl; ///< The primary device control I/O base.
|
|
UINT16 PrimaryBase; ///< The primary device I/O base.
|
|
UINT16 PrimaryBusMaster; ///< The primary device bus master I/O base.
|
|
//
|
|
// Secondary Section
|
|
//
|
|
UINT8 SecondaryIrq; ///< The secondary device IRQ.
|
|
UINT8 SecondaryReserved; ///< Reserved.
|
|
UINT16 SecondaryControl; ///< The secondary device control I/O base.
|
|
UINT16 SecondaryBase; ///< The secondary device I/O base.
|
|
UINT16 SecondaryBusMaster; ///< The secondary device bus master I/O base.
|
|
} EFI_LEGACY_INSTALL_PCI_HANDLER;
|
|
|
|
//
|
|
// Restore default pack value
|
|
//
|
|
#pragma pack()
|
|
|
|
#endif /* _FRAMEWORK_LEGACY_16_H_ */
|