mirror of https://github.com/acidanthera/audk.git
95 lines
3.4 KiB
C
95 lines
3.4 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmGicLib.h>
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#include <Library/ArmMPCoreMailBoxLib.h>
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#include <Chipset/ArmV7.h>
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#include "PrePeiCore.h"
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extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
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/*
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* This is the main function for secondary cores. They loop around until a non Null value is written to
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* SYS_FLAGS register.The SYS_FLAGS register is platform specific.
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* Note:The secondary cores, while executing secondary_main, assumes that:
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* : SGI 0 is configured as Non-secure interrupt
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* : Priority Mask is configured to allow SGI 0
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* : Interrupt Distributor and CPU interfaces are enabled
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*
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*/
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN MpId
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)
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{
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// Function pointer to Secondary Core entry point
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VOID (*secondary_start)(VOID);
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UINTN secondary_entry_addr=0;
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// Clear Secondary cores MailBox
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ArmClearMPCoreMailbox();
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while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
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}
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secondary_start = (VOID (*)())secondary_entry_addr;
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// Jump to secondary core entry point.
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secondary_start();
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// The secondaries shouldn't reach here
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ASSERT(FALSE);
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}
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VOID
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EFIAPI
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PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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// Enable the GIC Distributor
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ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
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// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
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if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
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// Sending SGI to all the Secondary CPU interfaces
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ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
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SecCoreData.StackBase = SecCoreData.TemporaryRamBase;
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SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
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// Jump to PEI core entry point
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(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
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}
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