mirror of https://github.com/acidanthera/audk.git
126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/** @file
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Quark platform specific information.
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Copyright (c) 2013 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "Uefi.h"
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#ifndef __PLATFORM_H__
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#define __PLATFORM_H__
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//
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// Constant definition
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//
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#define MAX_SMRAM_RANGES 4
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#define MAX_NODE 1
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#define QUARK_STAGE1_IMAGE_TYPE_MASK 0xF0
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#define QUARK_STAGE1_BOOT_IMAGE_TYPE 0x00 // Stage1 Boot images 0x00 -> 0x0F.
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#define QUARK_STAGE1_RECOVERY_IMAGE_TYPE 0x10 // Stage1 Recovery images 0x10 -> 0x1F.
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#define QUARK_BOOTROM_BASE_ADDRESS 0xFFFE0000 // Base address of Quark ROM in memory map.
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#define QUARK_BOOTROM_SIZE_BYTES 0x20000 // Quark ROM is 128KB.
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#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address.
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#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM.
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//
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// Gpio to be used to assert / deassert PCI express PERST# signal.
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//
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#define PCIEXP_PERST_RESUMEWELL_GPIO 3
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//
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// Minimum time in microseconds for assertion of PERST# signal.
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//
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#define PCIEXP_PERST_MIN_ASSERT_US 100
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//
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// Microsecond delay post issueing common lane reset.
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//
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#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1
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//
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// Microsecond delay to wait for PLL to lock.
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//
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#define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80
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//
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// Microsecond delay post issueing sideband interface reset.
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//
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#define PCIEXP_DELAY_US_POST_SBI_RESET 20
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//
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// Microsecond delay post deasserting PERST#.
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//
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#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10
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//
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// Catastrophic Trip point in degrees Celsius for this platform.
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//
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#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105
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//
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// Platform flash update LED common definitions.
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//
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#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT 7
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#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA (1000 * 1000) // In Microseconds for EFI_STALL.
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//
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// This structure stores the base and size of the ACPI reserved memory used when
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// resuming from S3. This region must be allocated by the platform code.
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//
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typedef struct {
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UINT32 AcpiReservedMemoryBase;
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UINT32 AcpiReservedMemorySize;
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UINT32 SystemMemoryLength;
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} RESERVED_ACPI_S3_RANGE;
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#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))
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//
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// Define valid platform types.
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// First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition
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// and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION.
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// Value shown for supported platforms to help sanity checking with build tools
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// and ACPI method usage.
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//
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typedef enum {
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TypeUnknown = 0, // !!! SHOULD BE THE FIRST ENTRY !!!
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QuarkEmulation = 1,
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ClantonPeakSVP = 2,
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KipsBay = 3,
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CrossHill = 4,
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ClantonHill = 5,
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Galileo = 6,
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TypePlatformRsv7 = 7,
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GalileoGen2 = 8,
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TypePlatformMax // !!! SHOULD BE THE LAST ENTRY !!!
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} EFI_PLATFORM_TYPE;
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#define EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION \
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L"TypeUnknown",\
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L"QuarkEmulation",\
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L"ClantonPeakSVP",\
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L"KipsBay",\
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L"CrossHill",\
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L"ClantonHill",\
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L"Galileo",\
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L"TypePlatformRsv7",\
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L"GalileoGen2",\
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typedef struct {
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UINT32 EntryOffset;
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UINT8 ImageIndex;
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} QUARK_EDKII_STAGE1_HEADER;
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#endif
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