mirror of https://github.com/acidanthera/audk.git
185 lines
8.0 KiB
C
185 lines
8.0 KiB
C
/** @file
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Virtual Memory Management Services to set or clear the memory encryption bit
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
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**/
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#ifndef __VIRTUAL_MEMORY__
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#define __VIRTUAL_MEMORY__
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#include <Uefi.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#define SYS_CODE64_SEL 0x38
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#pragma pack(1)
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Reserved:1; // Reserved
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UINT64 MustBeZero:2; // Must Be Zero
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 4KB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 PAT:1; //
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_4K_ENTRY;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:8; // Must be zero;
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UINT64 PageTableBaseAddress:31; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:17; // Must be zero;
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UINT64 PageTableBaseAddress:22; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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#pragma pack()
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)
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#define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)
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#define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)
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#define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)
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#define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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/**
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This function clears memory encryption bit for the memory region specified by PhysicalAddress
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and length from the current page table context.
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@param[in] PhysicalAddress The physical address that is the start address of a memory region.
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@param[in] Length The length of memory region
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@param[in] Flush Flush the caches before applying the encryption mask
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@retval RETURN_SUCCESS The attributes were cleared for the memory region.
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@retval RETURN_INVALID_PARAMETER Number of pages is zero.
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@retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is not supported
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**/
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RETURN_STATUS
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EFIAPI
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InternalMemEncryptSevSetMemoryDecrypted (
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IN PHYSICAL_ADDRESS Cr3BaseAddress,
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IN PHYSICAL_ADDRESS PhysicalAddress,
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IN UINT64 Length,
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IN BOOLEAN CacheFlush
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);
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/**
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This function sets memory encryption bit for the memory region specified by
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PhysicalAddress and length from the current page table context.
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@param[in] PhysicalAddress The physical address that is the start address
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of a memory region.
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@param[in] Length The length of memory region
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@param[in] Flush Flush the caches before applying the
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encryption mask
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@retval RETURN_SUCCESS The attributes were cleared for the memory region.
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@retval RETURN_INVALID_PARAMETER Number of pages is zero.
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@retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is
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not supported
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**/
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RETURN_STATUS
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EFIAPI
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InternalMemEncryptSevSetMemoryEncrypted (
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IN PHYSICAL_ADDRESS Cr3BaseAddress,
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IN PHYSICAL_ADDRESS PhysicalAddress,
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IN UINT64 Length,
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IN BOOLEAN CacheFlush
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);
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#endif
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