mirror of https://github.com/acidanthera/audk.git
123 lines
3.2 KiB
ArmAsm
123 lines
3.2 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
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#
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# All rights reserved. This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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.globl ASM_PFX(Cp15IdCode)
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.globl ASM_PFX(Cp15CacheInfo)
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.globl ASM_PFX(ArmEnableInterrupts)
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.globl ASM_PFX(ArmDisableInterrupts)
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.globl ASM_PFX(ArmGetInterruptState)
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.globl ASM_PFX(ArmEnableFiq)
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.globl ASM_PFX(ArmDisableFiq)
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.globl ASM_PFX(ArmGetFiqState)
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.globl ASM_PFX(ArmInvalidateTlb)
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.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
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.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
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.globl ASM_PFX(ArmSetDomainAccessControl)
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.globl ASM_PFX(CPSRMaskInsert)
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.globl ASM_PFX(CPSRRead)
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.globl ASM_PFX(ReadCCSIDR)
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.globl ASM_PFX(ReadCLIDR)
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#------------------------------------------------------------------------------
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ASM_PFX(Cp15IdCode):
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mrc p15,0,R0,c0,c0,0
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bx LR
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ASM_PFX(Cp15CacheInfo):
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mrc p15,0,R0,c0,c0,1
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bx LR
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ASM_PFX(ArmEnableInterrupts):
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cpsie i
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bx LR
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ASM_PFX(ArmDisableInterrupts):
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cpsid i
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bx LR
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ASM_PFX(ArmGetInterruptState):
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mrs R0,CPSR
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tst R0,#0x80 @Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmEnableFiq):
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cpsie f
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bx LR
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ASM_PFX(ArmDisableFiq):
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cpsid f
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bx LR
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ASM_PFX(ArmGetFiqState):
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mrs R0,CPSR
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tst R0,#0x30 @Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmInvalidateTlb):
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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isb
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bx lr
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ASM_PFX(ArmSetTranslationTableBaseAddress):
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mcr p15,0,r0,c2,c0,0
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isb
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bx lr
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ASM_PFX(ArmGetTranslationTableBaseAddress):
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mrc p15,0,r0,c2,c0,0
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bx lr
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ASM_PFX(ArmSetDomainAccessControl):
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mcr p15,0,r0,c3,c0,0
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isb
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bx lr
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ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
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stmfd sp!, {r4-r12, lr} @ save all the banked registers
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mov r3, sp @ copy the stack pointer into a non-banked register
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mrs r2, cpsr @ read the cpsr
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bic r2, r2, r0 @ clear mask in the cpsr
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and r1, r1, r0 @ clear bits outside the mask in the input
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orr r2, r2, r1 @ set field
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msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
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mov sp, r3 @ restore stack pointer
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ldmfd sp!, {r4-r12, lr} @ restore registers
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bx lr @ return (hopefully thumb-safe!)
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ASM_PFX(CPSRRead):
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mrs r0, cpsr
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bx lr
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ASM_PFX(ReadCCSIDR):
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mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
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isb
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mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
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bx lr
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ASM_PFX(ReadCLIDR):
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mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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