mirror of https://github.com/acidanthera/audk.git
eaffa1d7ff
The implementation of this new behavior aligns with the guidelines outlined in the Intel SDM. Following a power-up or RESET of an MP system, system hardware dynamically selects one of the processors on the system bus as the BSP. The remaining processors are designated as APs. The APs complete a minimal self-configuration, then wait for a startup signal (a SIPI message) from the BSP processor. Additionally, the MP protocol is executed only after a power-up or RESET. If the MP protocol has completed and a BSP is chosen, subsequent INITs (either to a specific processor or system wide) do not cause the MP protocol to be repeated. Instead, each logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) to determine whether it should execute the BIOS boot-strap code (if it is the BSP) or enter a wait-for-SIPI state (if it is an AP). Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> |
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| .. | ||
| BaseRiscV64CpuExceptionHandlerLib | ||
| BaseRiscV64CpuTimerLib | ||
| BaseRiscVMmuLib | ||
| BaseXApicLib | ||
| BaseXApicX2ApicLib | ||
| CcExitLibNull | ||
| CpuCacheInfoLib | ||
| CpuCommonFeaturesLib | ||
| CpuExceptionHandlerLib | ||
| CpuPageTableLib | ||
| CpuTimerLib | ||
| MicrocodeLib | ||
| MmSaveStateLib | ||
| MpInitLib | ||
| MpInitLibUp | ||
| MtrrLib | ||
| PlatformSecLibNull | ||
| RegisterCpuFeaturesLib | ||
| SecPeiDxeTimerLibUefiCpu | ||
| SmmCpuFeaturesLib | ||
| SmmCpuPlatformHookLibNull | ||
| SmmCpuRendezvousLib | ||