notepad-plus-plus/lexilla/test/examples/verilog/SciTE.properties

lexer.*.vh=verilog

keywords.*.vh= \
always and assign automatic \
begin buf bufif0 bufif1 \
case casex casez cell cmos config \
deassign default defparam design disable \
edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event \
for force forever fork function \
generate genvar \
highz0 highz1 \
if ifnone incdir include initial inout input instance integer \
join \
large liblist library localparam \
macromodule medium module \
nand negedge nmos nor noshowcancelled not notif0 notif1 \
or output \
parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent \
rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 \
scalared showcancelled signed small specify specparam strong0 strong1 supply0 supply1 \
table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg \
unsigned use uwire \
vectored \
wait wand weak0 weak1 while wire wor \
xnor xor
keywords2.*.vh=special
keywords3.*.vh= \
$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane \
$bitstoreal \
$countdrivers \
$display $displayb $displayh $displayo \
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform \
$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars \
$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $feof $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite \
$getpattern \
$history $hold \
$incsave $input $itor \
$key \
$list $log \
$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro \
$nochange $nokey $nolog \
$period $printtimescale \
$q_add $q_exam $q_full $q_initialize $q_remove \
$random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi \
$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane \
$test$plusargs $time $timeformat $timeskew \
$ungetc $unsigned \
$value$plusargs \
$width $writeb $writeh $write $writeo
keywords4.*.vh=my_var
keywords5.*.vh=synopsys parallel_case infer_mux TODO

fold=1
fold.compact=0
fold.comment=1
fold.preprocessor=1
fold.at.else=1
fold.verilog.flags=1  # fold module definitions
lexer.verilog.track.preprocessor=1
lexer.verilog.update.preprocessor=1
lexer.verilog.portstyling=1
lexer.verilog.fold.preprocessor.else=1