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36 lines
714 B
Plaintext
36 lines
714 B
Plaintext
entity ent1 is
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end entity ent1;
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architecture rtl of ent1 is
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component compo1 is
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PORT ( Reset_s : out std_logic);
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end component compo1;
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component reset_controller is -- comment
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PORT -- comment
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( Reset_s : out std_logic);
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end component reset_controller; -- comment
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begin
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compo1_inst : compo1
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PORT MAP ( Reset_s =>open);
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rst_controller_inst : component reset_controller
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PORT MAP ( Reset_s => open); -- comment
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proc1: process (reset_reset_n, clk_clk)
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begin
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end process;
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block1: block is
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begin
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end block;
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comp_per_entity : entity work.doing_so port map ( Reset_s => open
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);
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end architecture rtl; -- of ent1
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