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ed4bb1a93e
Use new interfaces SCI_FORMATRANGEFULL, SCI_GETTEXTRANGEFULL, SCI_FINDTEXTFULL from scintilla 5.2.3 Close #11734
599 lines
20 KiB
C++
599 lines
20 KiB
C++
// Scintilla source code edit control
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/** @file LexVHDL.cxx
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** Lexer for VHDL
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** Written by Phil Reid,
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** Based on:
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** - The Verilog Lexer by Avi Yegudin
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** - The Fortran Lexer by Chuan-jian Shen
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** - The C++ lexer by Neil Hodgson
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**/
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// Copyright 1998-2002 by Neil Hodgson <neilh@scintilla.org>
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// The License.txt file describes the conditions under which this software may be distributed.
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#include <stdlib.h>
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#include <string.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <assert.h>
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#include <ctype.h>
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#include <string>
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#include <string_view>
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#include "ILexer.h"
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#include "Scintilla.h"
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#include "SciLexer.h"
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#include "WordList.h"
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#include "LexAccessor.h"
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#include "Accessor.h"
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#include "StyleContext.h"
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#include "CharacterSet.h"
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#include "LexerModule.h"
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using namespace Lexilla;
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static void ColouriseVHDLDoc(
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Sci_PositionU startPos,
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Sci_Position length,
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int initStyle,
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WordList *keywordlists[],
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Accessor &styler);
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/***************************************/
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static inline bool IsAWordChar(const int ch) {
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return (ch < 0x80) && (isalnum(ch) || ch == '.' || ch == '_' );
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}
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/***************************************/
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static inline bool IsAWordStart(const int ch) {
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return (ch < 0x80) && (isalnum(ch) || ch == '_');
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}
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/***************************************/
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static inline bool IsABlank(unsigned int ch) {
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return (ch == ' ') || (ch == 0x09) || (ch == 0x0b) ;
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}
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/***************************************/
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static void ColouriseVHDLDoc(
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Sci_PositionU startPos,
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Sci_Position length,
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int initStyle,
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WordList *keywordlists[],
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Accessor &styler)
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{
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WordList &Keywords = *keywordlists[0];
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WordList &Operators = *keywordlists[1];
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WordList &Attributes = *keywordlists[2];
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WordList &Functions = *keywordlists[3];
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WordList &Packages = *keywordlists[4];
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WordList &Types = *keywordlists[5];
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WordList &User = *keywordlists[6];
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StyleContext sc(startPos, length, initStyle, styler);
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bool isExtendedId = false; // true when parsing an extended identifier
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while (sc.More())
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{
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bool advance = true;
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// Determine if the current state should terminate.
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if (sc.state == SCE_VHDL_OPERATOR) {
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sc.SetState(SCE_VHDL_DEFAULT);
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} else if (sc.state == SCE_VHDL_NUMBER) {
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if (!IsAWordChar(sc.ch) && (sc.ch != '#')) {
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sc.SetState(SCE_VHDL_DEFAULT);
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}
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} else if (sc.state == SCE_VHDL_IDENTIFIER) {
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if (!isExtendedId && (!IsAWordChar(sc.ch) || (sc.ch == '.'))) {
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char s[100];
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sc.GetCurrentLowered(s, sizeof(s));
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if (Keywords.InList(s)) {
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sc.ChangeState(SCE_VHDL_KEYWORD);
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} else if (Operators.InList(s)) {
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sc.ChangeState(SCE_VHDL_STDOPERATOR);
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} else if (Attributes.InList(s)) {
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sc.ChangeState(SCE_VHDL_ATTRIBUTE);
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} else if (Functions.InList(s)) {
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sc.ChangeState(SCE_VHDL_STDFUNCTION);
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} else if (Packages.InList(s)) {
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sc.ChangeState(SCE_VHDL_STDPACKAGE);
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} else if (Types.InList(s)) {
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sc.ChangeState(SCE_VHDL_STDTYPE);
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} else if (User.InList(s)) {
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sc.ChangeState(SCE_VHDL_USERWORD);
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}
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sc.SetState(SCE_VHDL_DEFAULT);
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} else if (isExtendedId && ((sc.ch == '\\') || sc.atLineEnd)) {
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// extended identifiers are terminated by backslash, check for end of line in case we have invalid syntax
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isExtendedId = false;
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sc.ForwardSetState(SCE_VHDL_DEFAULT);
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advance = false;
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}
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} else if (sc.state == SCE_VHDL_COMMENT || sc.state == SCE_VHDL_COMMENTLINEBANG) {
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if (sc.atLineEnd) {
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sc.SetState(SCE_VHDL_DEFAULT);
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}
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} else if (sc.state == SCE_VHDL_STRING) {
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if (sc.ch == '"') {
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advance = false;
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sc.Forward();
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if (sc.ch == '"')
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sc.Forward();
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else
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sc.SetState(SCE_VHDL_DEFAULT);
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} else if (sc.atLineEnd) {
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advance = false;
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sc.ChangeState(SCE_VHDL_STRINGEOL);
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sc.ForwardSetState(SCE_VHDL_DEFAULT);
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}
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} else if (sc.state == SCE_VHDL_BLOCK_COMMENT){
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if(sc.ch == '*' && sc.chNext == '/'){
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advance = false;
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sc.Forward();
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sc.ForwardSetState(SCE_VHDL_DEFAULT);
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}
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}
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// Determine if a new state should be entered.
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if (sc.state == SCE_VHDL_DEFAULT) {
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if (IsADigit(sc.ch) || (sc.ch == '.' && IsADigit(sc.chNext))) {
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sc.SetState(SCE_VHDL_NUMBER);
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} else if (IsAWordStart(sc.ch)) {
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sc.SetState(SCE_VHDL_IDENTIFIER);
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} else if (sc.Match('-', '-')) {
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if (sc.Match("--!")) // Nice to have a different comment style
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sc.SetState(SCE_VHDL_COMMENTLINEBANG);
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else
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sc.SetState(SCE_VHDL_COMMENT);
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} else if (sc.Match('/', '*')){
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sc.SetState(SCE_VHDL_BLOCK_COMMENT);
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} else if (sc.ch == '"') {
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sc.SetState(SCE_VHDL_STRING);
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} else if (sc.ch == '\'') {
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if (sc.GetRelative(2) == '\''){
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if (sc.chNext != '(' || sc.GetRelative(4) != '\''){
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// Can only be a character literal
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sc.SetState(SCE_VHDL_STRING);
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sc.Forward();
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sc.Forward();
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sc.ForwardSetState(SCE_VHDL_DEFAULT);
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advance = false;
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} // else can be a tick or a character literal, need more context, eg.: identifier'('x')
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} // else can only be a tick
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} else if (sc.ch == '\\') {
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isExtendedId = true;
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sc.SetState(SCE_VHDL_IDENTIFIER);
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} else if (isoperator(static_cast<char>(sc.ch))) {
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sc.SetState(SCE_VHDL_OPERATOR);
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}
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}
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if (advance)
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sc.Forward();
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}
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sc.Complete();
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}
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//=============================================================================
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static bool IsCommentLine(Sci_Position line, Accessor &styler) {
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Sci_Position pos = styler.LineStart(line);
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Sci_Position eol_pos = styler.LineStart(line + 1) - 1;
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for (Sci_Position i = pos; i < eol_pos; i++) {
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char ch = styler[i];
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char chNext = styler[i+1];
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if ((ch == '-') && (chNext == '-'))
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return true;
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else if (ch != ' ' && ch != '\t')
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return false;
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}
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return false;
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}
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static bool IsCommentBlockStart(Sci_Position line, Accessor &styler)
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{
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Sci_Position pos = styler.LineStart(line);
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Sci_Position eol_pos = styler.LineStart(line + 1) - 1;
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for (Sci_Position i = pos; i < eol_pos; i++) {
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char ch = styler[i];
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char chNext = styler[i+1];
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char style = styler.StyleAt(i);
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if ((style == SCE_VHDL_BLOCK_COMMENT) && (ch == '/') && (chNext == '*'))
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return true;
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}
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return false;
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}
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static bool IsCommentBlockEnd(Sci_Position line, Accessor &styler)
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{
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Sci_Position pos = styler.LineStart(line);
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Sci_Position eol_pos = styler.LineStart(line + 1) - 1;
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for (Sci_Position i = pos; i < eol_pos; i++) {
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char ch = styler[i];
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char chNext = styler[i+1];
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char style = styler.StyleAt(i);
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if ((style == SCE_VHDL_BLOCK_COMMENT) && (ch == '*') && (chNext == '/'))
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return true;
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}
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return false;
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}
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static bool IsCommentStyle(char style)
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{
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return style == SCE_VHDL_BLOCK_COMMENT || style == SCE_VHDL_COMMENT || style == SCE_VHDL_COMMENTLINEBANG;
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}
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//=============================================================================
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// Folding the code
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static void FoldNoBoxVHDLDoc(
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Sci_PositionU startPos,
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Sci_Position length,
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int,
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Accessor &styler)
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{
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// Decided it would be smarter to have the lexer have all keywords included. Therefore I
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// don't check if the style for the keywords that I use to adjust the levels.
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char words[] =
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"architecture begin block case component else elsif end entity for generate loop package process record then "
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"procedure protected function when units";
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WordList keywords;
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keywords.Set(words);
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bool foldComment = styler.GetPropertyInt("fold.comment", 1) != 0;
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bool foldCompact = styler.GetPropertyInt("fold.compact", 1) != 0;
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bool foldAtElse = styler.GetPropertyInt("fold.at.else", 1) != 0;
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bool foldAtBegin = styler.GetPropertyInt("fold.at.Begin", 1) != 0;
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bool foldAtParenthese = styler.GetPropertyInt("fold.at.Parenthese", 1) != 0;
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//bool foldAtWhen = styler.GetPropertyInt("fold.at.When", 1) != 0; //< fold at when in case statements
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int visibleChars = 0;
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Sci_PositionU endPos = startPos + length;
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Sci_Position lineCurrent = styler.GetLine(startPos);
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int levelCurrent = SC_FOLDLEVELBASE;
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if(lineCurrent > 0)
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levelCurrent = styler.LevelAt(lineCurrent-1) >> 16;
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//int levelMinCurrent = levelCurrent;
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int levelMinCurrentElse = levelCurrent; ///< Used for folding at 'else'
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int levelMinCurrentBegin = levelCurrent; ///< Used for folding at 'begin'
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int levelNext = levelCurrent;
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/***************************************/
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Sci_Position lastStart = 0;
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char prevWord[32] = "";
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/***************************************/
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// Find prev word
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// The logic for going up or down a level depends on a the previous keyword
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// This code could be cleaned up.
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Sci_Position end = 0;
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Sci_PositionU j;
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for(j = startPos; j>0; j--)
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{
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char ch = styler.SafeGetCharAt(j);
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char chPrev = styler.SafeGetCharAt(j-1);
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int style = styler.StyleAt(j);
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int stylePrev = styler.StyleAt(j-1);
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if ((!IsCommentStyle(style)) && (stylePrev != SCE_VHDL_STRING))
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{
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if(IsAWordChar(chPrev) && !IsAWordChar(ch))
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{
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end = j-1;
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}
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}
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if ((!IsCommentStyle(style)) && (style != SCE_VHDL_STRING))
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{
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if(!IsAWordChar(chPrev) && IsAWordStart(ch) && (end != 0))
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{
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char s[32];
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Sci_PositionU k;
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for(k=0; (k<31 ) && (k<end-j+1 ); k++) {
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s[k] = static_cast<char>(tolower(styler[j+k]));
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}
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s[k] = '\0';
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if(keywords.InList(s)) {
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strcpy(prevWord, s);
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break;
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}
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}
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}
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}
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for(j=j+static_cast<Sci_PositionU>(strlen(prevWord)); j<endPos; j++)
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{
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char ch = styler.SafeGetCharAt(j);
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int style = styler.StyleAt(j);
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if ((!IsCommentStyle(style)) && (style != SCE_VHDL_STRING))
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{
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if((ch == ';') && (strcmp(prevWord, "end") == 0))
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{
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strcpy(prevWord, ";");
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}
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}
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}
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char chNext = styler[startPos];
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char chPrev = '\0';
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char chNextNonBlank;
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int styleNext = styler.StyleAt(startPos);
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//Platform::DebugPrintf("Line[%04d] Prev[%20s] ************************* Level[%x]\n", lineCurrent+1, prevWord, levelCurrent);
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/***************************************/
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for (Sci_PositionU i = startPos; i < endPos; i++)
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{
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char ch = chNext;
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chNext = styler.SafeGetCharAt(i + 1);
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chPrev = styler.SafeGetCharAt(i - 1);
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chNextNonBlank = chNext;
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Sci_PositionU j = i+1;
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while(IsABlank(chNextNonBlank) && j<endPos)
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{
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j ++ ;
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chNextNonBlank = styler.SafeGetCharAt(j);
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}
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int style = styleNext;
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styleNext = styler.StyleAt(i + 1);
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bool atEOL = (ch == '\r' && chNext != '\n') || (ch == '\n');
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if (foldComment && atEOL)
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{
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if(IsCommentLine(lineCurrent, styler))
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{
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if(!IsCommentLine(lineCurrent-1, styler) && IsCommentLine(lineCurrent+1, styler))
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{
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levelNext++;
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}
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else if(IsCommentLine(lineCurrent-1, styler) && !IsCommentLine(lineCurrent+1, styler))
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{
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levelNext--;
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}
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}
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else
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{
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if (IsCommentBlockStart(lineCurrent, styler) && !IsCommentBlockEnd(lineCurrent, styler))
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{
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levelNext++;
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}
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else if (IsCommentBlockEnd(lineCurrent, styler) && !IsCommentBlockStart(lineCurrent, styler))
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{
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levelNext--;
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}
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}
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}
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if ((style == SCE_VHDL_OPERATOR) && foldAtParenthese)
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{
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if(ch == '(') {
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levelNext++;
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} else if (ch == ')') {
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levelNext--;
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}
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}
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if ((!IsCommentStyle(style)) && (style != SCE_VHDL_STRING))
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{
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if((ch == ';') && (strcmp(prevWord, "end") == 0))
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{
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strcpy(prevWord, ";");
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}
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if(!IsAWordChar(chPrev) && IsAWordStart(ch))
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{
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lastStart = i;
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}
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if(IsAWordChar(ch) && !IsAWordChar(chNext)) {
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char s[32];
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Sci_PositionU k;
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for(k=0; (k<31 ) && (k<i-lastStart+1 ); k++) {
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s[k] = static_cast<char>(tolower(styler[lastStart+k]));
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}
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s[k] = '\0';
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if(keywords.InList(s))
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{
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if (
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strcmp(s, "architecture") == 0 ||
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strcmp(s, "case") == 0 ||
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strcmp(s, "block") == 0 ||
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strcmp(s, "loop") == 0 ||
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strcmp(s, "package") ==0 ||
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strcmp(s, "process") == 0 ||
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strcmp(s, "protected") == 0 ||
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strcmp(s, "record") == 0 ||
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strcmp(s, "then") == 0 ||
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strcmp(s, "units") == 0)
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{
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if (strcmp(prevWord, "end") != 0)
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{
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if (levelMinCurrentElse > levelNext) {
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levelMinCurrentElse = levelNext;
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}
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levelNext++;
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}
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} else if (strcmp(s, "generate") == 0){
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if (strcmp(prevWord, "end") != 0 &&
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strcmp(prevWord, "else") != 0 && // vhdl08 else generate
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strcmp(prevWord, "case") != 0) // vhdl08 case generate
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{
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if (levelMinCurrentElse > levelNext) {
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levelMinCurrentElse = levelNext;
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}
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levelNext++;
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}
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} else if (
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strcmp(s, "component") == 0 ||
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strcmp(s, "entity") == 0 ||
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strcmp(s, "configuration") == 0 )
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{
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if (strcmp(prevWord, "end") != 0)
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{ // check for instantiated unit by backward searching for the colon.
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Sci_PositionU pos = lastStart;
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char chAtPos=0, styleAtPos;
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do{// skip white spaces
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if(!pos)
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break;
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pos--;
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styleAtPos = styler.StyleAt(pos);
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chAtPos = styler.SafeGetCharAt(pos);
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}while(pos &&
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(chAtPos == ' ' || chAtPos == '\t' ||
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chAtPos == '\n' || chAtPos == '\r' ||
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IsCommentStyle(styleAtPos)));
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// check for a colon (':') before the instantiated units "entity", "component" or "configuration". Don't fold thereafter.
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if (chAtPos != ':')
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{
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if (levelMinCurrentElse > levelNext) {
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levelMinCurrentElse = levelNext;
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}
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levelNext++;
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}
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}
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} else if (
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strcmp(s, "procedure") == 0 ||
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strcmp(s, "function") == 0)
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{
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if (strcmp(prevWord, "end") != 0) // check for "end procedure" etc.
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{ // This code checks to see if the procedure / function is a definition within a "package"
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// rather than the actual code in the body.
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int BracketLevel = 0;
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for(Sci_Position pos=i+1; pos<styler.Length(); pos++)
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{
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int styleAtPos = styler.StyleAt(pos);
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char chAtPos = styler.SafeGetCharAt(pos);
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if(chAtPos == '(') BracketLevel++;
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if(chAtPos == ')') BracketLevel--;
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if(
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(BracketLevel == 0) &&
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(!IsCommentStyle(styleAtPos)) &&
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(styleAtPos != SCE_VHDL_STRING) &&
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!iswordchar(styler.SafeGetCharAt(pos-1)) &&
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(chAtPos|' ')=='i' && (styler.SafeGetCharAt(pos+1)|' ')=='s' &&
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!iswordchar(styler.SafeGetCharAt(pos+2)))
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{
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if (levelMinCurrentElse > levelNext) {
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levelMinCurrentElse = levelNext;
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}
|
|
levelNext++;
|
|
break;
|
|
}
|
|
if((BracketLevel == 0) && (chAtPos == ';'))
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
} else if (strcmp(s, "end") == 0) {
|
|
levelNext--;
|
|
} else if(strcmp(s, "elsif") == 0) { // elsif is followed by then or generate so folding occurs correctly
|
|
levelNext--;
|
|
} else if (strcmp(s, "else") == 0) {
|
|
if(strcmp(prevWord, "when") != 0) // ignore a <= x when y else z;
|
|
{
|
|
levelMinCurrentElse = levelNext - 1; // VHDL else is all on its own so just dec. the min level
|
|
}
|
|
} else if(
|
|
((strcmp(s, "begin") == 0) && (strcmp(prevWord, "architecture") == 0)) ||
|
|
((strcmp(s, "begin") == 0) && (strcmp(prevWord, "function") == 0)) ||
|
|
((strcmp(s, "begin") == 0) && (strcmp(prevWord, "procedure") == 0)) ||
|
|
((strcmp(s, "begin") == 0) && (strcmp(prevWord, "generate") == 0)))
|
|
{
|
|
levelMinCurrentBegin = levelNext - 1;
|
|
}
|
|
//Platform::DebugPrintf("Line[%04d] Prev[%20s] Cur[%20s] Level[%x]\n", lineCurrent+1, prevWord, s, levelCurrent);
|
|
strcpy(prevWord, s);
|
|
}
|
|
}
|
|
}
|
|
if (atEOL) {
|
|
int levelUse = levelCurrent;
|
|
|
|
if (foldAtElse && (levelMinCurrentElse < levelUse)) {
|
|
levelUse = levelMinCurrentElse;
|
|
}
|
|
if (foldAtBegin && (levelMinCurrentBegin < levelUse)) {
|
|
levelUse = levelMinCurrentBegin;
|
|
}
|
|
int lev = levelUse | levelNext << 16;
|
|
if (visibleChars == 0 && foldCompact)
|
|
lev |= SC_FOLDLEVELWHITEFLAG;
|
|
|
|
if (levelUse < levelNext)
|
|
lev |= SC_FOLDLEVELHEADERFLAG;
|
|
if (lev != styler.LevelAt(lineCurrent)) {
|
|
styler.SetLevel(lineCurrent, lev);
|
|
}
|
|
//Platform::DebugPrintf("Line[%04d] ---------------------------------------------------- Level[%x]\n", lineCurrent+1, levelCurrent);
|
|
lineCurrent++;
|
|
levelCurrent = levelNext;
|
|
//levelMinCurrent = levelCurrent;
|
|
levelMinCurrentElse = levelCurrent;
|
|
levelMinCurrentBegin = levelCurrent;
|
|
visibleChars = 0;
|
|
}
|
|
/***************************************/
|
|
if (!isspacechar(ch)) visibleChars++;
|
|
}
|
|
|
|
/***************************************/
|
|
// Platform::DebugPrintf("Line[%04d] ---------------------------------------------------- Level[%x]\n", lineCurrent+1, levelCurrent);
|
|
}
|
|
|
|
//=============================================================================
|
|
static void FoldVHDLDoc(Sci_PositionU startPos, Sci_Position length, int initStyle, WordList *[],
|
|
Accessor &styler) {
|
|
FoldNoBoxVHDLDoc(startPos, length, initStyle, styler);
|
|
}
|
|
|
|
//=============================================================================
|
|
static const char * const VHDLWordLists[] = {
|
|
"Keywords",
|
|
"Operators",
|
|
"Attributes",
|
|
"Standard Functions",
|
|
"Standard Packages",
|
|
"Standard Types",
|
|
"User Words",
|
|
0,
|
|
};
|
|
|
|
|
|
LexerModule lmVHDL(SCLEX_VHDL, ColouriseVHDLDoc, "vhdl", FoldVHDLDoc, VHDLWordLists);
|
|
|
|
|
|
// Keyword:
|
|
// access after alias all architecture array assert attribute begin block body buffer bus case component
|
|
// configuration constant disconnect downto else elsif end entity exit file for function generate generic
|
|
// group guarded if impure in inertial inout is label library linkage literal loop map new next null of
|
|
// on open others out package port postponed procedure process pure range record register reject report
|
|
// return select severity shared signal subtype then to transport type unaffected units until use variable
|
|
// wait when while with
|
|
//
|
|
// Operators:
|
|
// abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
|
|
//
|
|
// Attributes:
|
|
// left right low high ascending image value pos val succ pred leftof rightof base range reverse_range
|
|
// length delayed stable quiet transaction event active last_event last_active last_value driving
|
|
// driving_value simple_name path_name instance_name
|
|
//
|
|
// Std Functions:
|
|
// now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector
|
|
// to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left
|
|
// rotate_right resize to_integer to_unsigned to_signed std_match to_01
|
|
//
|
|
// Std Packages:
|
|
// std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed
|
|
// std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives
|
|
// vital_timing
|
|
//
|
|
// Std Types:
|
|
// boolean bit character severity_level integer real time delay_length natural positive string bit_vector
|
|
// file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic
|
|
// std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
|
|
//
|
|
|