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powerline
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Fix some style problems

This commit is contained in:
ZyX 2014-08-15 20:01:33 +04:00
parent 2f3d56887f
commit c316ef8e76
3 changed files with 3 additions and 3 deletions
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2
powerline/lib/vcs/__init__.py
View File

@ -194,7 +194,7 @@ class TreeStatusCache(dict):
if self.tw(key, logger=logger, ignore_event=getattr(repo, 'ignore_event', None)): if self.tw(key, logger=logger, ignore_event=getattr(repo, 'ignore_event', None)):
self.pop(key, None) self.pop(key, None)
except OSError as e: except OSError as e:
logger.warn('Failed to check %s for changes, with error: %s'% key, e) logger.warn('Failed to check %s for changes, with error: %s' % key, e)
return self.cache_and_get(key, repo.status) return self.cache_and_get(key, repo.status)

2
powerline/lint/__init__.py
View File

@ -1252,7 +1252,7 @@ segment_spec = Spec(
).func(check_full_segment_data) ).func(check_full_segment_data)
sub_segments_spec.optional().list(segment_spec) sub_segments_spec.optional().list(segment_spec)
segments_spec = Spec().optional().list(segment_spec).copy segments_spec = Spec().optional().list(segment_spec).copy
segdict_spec=Spec( segdict_spec = Spec(
left=segments_spec().context_message('Error while loading segments from left side (key {key})'), left=segments_spec().context_message('Error while loading segments from left side (key {key})'),
right=segments_spec().context_message('Error while loading segments from right side (key {key})'), right=segments_spec().context_message('Error while loading segments from right side (key {key})'),
).func( ).func(

2
powerline/segments/common.py
View File

@ -1130,7 +1130,7 @@ def _get_battery(pl):
what, what,
dbus_interface=devinterface dbus_interface=devinterface
) )
if int(devget('Type'))!= 2: if int(devget('Type')) != 2:
pl.debug('Not using DBUS+UPower with {0}: invalid type', devpath) pl.debug('Not using DBUS+UPower with {0}: invalid type', devpath)
continue continue
if not bool(devget('IsPresent')): if not bool(devget('IsPresent')):