2021-02-09 14:58:01 +01:00
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;------------------------------------------------------------------------------ ;
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2023-03-01 07:09:52 +01:00
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; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
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2021-02-09 14:58:01 +01:00
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; MpEqu.inc
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;
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; Abstract:
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;
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; This is the equates file for Multiple Processor support
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;
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;-------------------------------------------------------------------------------
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%include "Nasm.inc"
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CPU_SWITCH_STATE_IDLE equ 0
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CPU_SWITCH_STATE_STORED equ 1
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CPU_SWITCH_STATE_LOADED equ 2
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;
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; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP
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;
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struc MP_ASSEMBLY_ADDRESS_MAP
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.RendezvousFunnelAddress CTYPE_UINTN 1
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.ModeEntryOffset CTYPE_UINTN 1
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.RendezvousFunnelSize CTYPE_UINTN 1
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.RelocateApLoopFuncAddressGeneric CTYPE_UINTN 1
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.RelocateApLoopFuncSizeGeneric CTYPE_UINTN 1
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2023-03-01 07:09:53 +01:00
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.RelocateApLoopFuncAddressAmdSev CTYPE_UINTN 1
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.RelocateApLoopFuncSizeAmdSev CTYPE_UINTN 1
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2023-03-01 07:09:52 +01:00
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.ModeTransitionOffset CTYPE_UINTN 1
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.SwitchToRealNoNxOffset CTYPE_UINTN 1
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.SwitchToRealPM16ModeOffset CTYPE_UINTN 1
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.SwitchToRealPM16ModeSize CTYPE_UINTN 1
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2021-02-09 14:58:01 +01:00
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endstruc
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;
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; Equivalent NASM structure of IA32_DESCRIPTOR
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;
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struc IA32_DESCRIPTOR
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.Limit CTYPE_UINT16 1
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.Base CTYPE_UINTN 1
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endstruc
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;
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; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO
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;
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struc CPU_EXCHANGE_ROLE_INFO
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; State is defined as UINT8 in C header file
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; Define it as UINTN here to guarantee the fields that follow State
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; is naturally aligned. The structure layout doesn't change.
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.State CTYPE_UINTN 1
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.StackPointer CTYPE_UINTN 1
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.Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size
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.Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size
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endstruc
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;
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; Equivalent NASM structure of CPU_INFO_IN_HOB
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;
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struc CPU_INFO_IN_HOB
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.InitialApicId CTYPE_UINT32 1
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.ApicId CTYPE_UINT32 1
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.Health CTYPE_UINT32 1
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.ApTopOfStack CTYPE_UINT64 1
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endstruc
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;
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; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO
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;
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struc MP_CPU_EXCHANGE_INFO
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.StackStart: CTYPE_UINTN 1
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.StackSize: CTYPE_UINTN 1
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.CFunction: CTYPE_UINTN 1
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.GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size
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.IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size
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.BufferStart: CTYPE_UINTN 1
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.ModeOffset: CTYPE_UINTN 1
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.ApIndex: CTYPE_UINTN 1
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.CodeSegment: CTYPE_UINTN 1
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.DataSegment: CTYPE_UINTN 1
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.EnableExecuteDisable: CTYPE_UINTN 1
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.Cr3: CTYPE_UINTN 1
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.InitFlag: CTYPE_UINTN 1
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.CpuInfo: CTYPE_UINTN 1
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.NumApsExecuting: CTYPE_UINTN 1
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.CpuMpData: CTYPE_UINTN 1
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.InitializeFloatingPointUnits: CTYPE_UINTN 1
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.ModeTransitionMemory: CTYPE_UINT32 1
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.ModeTransitionSegment: CTYPE_UINT16 1
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.ModeHighMemory: CTYPE_UINT32 1
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.ModeHighSegment: CTYPE_UINT16 1
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.Enable5LevelPaging: CTYPE_BOOLEAN 1
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.SevEsIsEnabled: CTYPE_BOOLEAN 1
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2021-12-09 04:27:54 +01:00
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.SevSnpIsEnabled CTYPE_BOOLEAN 1
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2021-02-09 14:58:01 +01:00
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.GhcbBase: CTYPE_UINTN 1
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UefiCpuPkg/MpInitLib: use BSP to do extended topology check
During AP bringup, just after switching to long mode, APs will do some
cpuid calls to verify that the extended topology leaf (0xB) is available
so they can fetch their x2 APIC IDs from it. In the case of SEV-ES,
these cpuid instructions must be handled by direct use of the GHCB MSR
protocol to fetch the values from the hypervisor, since a #VC handler
is not yet available due to the AP's stack not being set up yet.
For SEV-SNP, rather than relying on the GHCB MSR protocol, it is
expected that these values would be obtained from the SEV-SNP CPUID
table instead. The actual x2 APIC ID (and 8-bit APIC IDs) would still
be fetched from hypervisor using the GHCB MSR protocol however, so
introducing support for the SEV-SNP CPUID table in that part of the AP
bring-up code would only be to handle the checks/validation of the
extended topology leaf.
Rather than introducing all the added complexity needed to handle these
checks via the CPUID table, instead let the BSP do the check in advance,
since it can make use of the #VC handler to avoid the need to scan the
SNP CPUID table directly, and add a flag in ExchangeInfo to communicate
the result of this check to APs.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Ray Ni <ray.ni@intel.com>
Suggested-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
2021-12-09 04:27:55 +01:00
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.ExtTopoAvail: CTYPE_BOOLEAN 1
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2021-02-09 14:58:01 +01:00
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endstruc
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2022-05-07 16:25:19 +02:00
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MP_CPU_EXCHANGE_INFO_OFFSET equ (Flat32Start - RendezvousFunnelProcStart)
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2021-02-09 14:58:01 +01:00
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%define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)
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