2016-07-20 16:44:39 +02:00
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; MpFuncs.nasm
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;
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; Abstract:
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;
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; This is the assembly code for MP support
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;
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;-------------------------------------------------------------------------------
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%include "MpEqu.inc"
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extern ASM_PFX(InitializeFloatingPointUnits)
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SECTION .text
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;-------------------------------------------------------------------------------------
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;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
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;procedure serializes all the AP processors through an Init sequence. It must be
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;noted that APs arrive here very raw...ie: real mode, no stack.
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;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
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;IS IN MACHINE CODE.
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;-------------------------------------------------------------------------------------
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global ASM_PFX(RendezvousFunnelProc)
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ASM_PFX(RendezvousFunnelProc):
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RendezvousFunnelProcStart:
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; At this point CS = 0x(vv00) and ip= 0x0.
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BITS 16
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mov ebp, eax ; save BIST information
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mov ax, cs
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mov ds, ax
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mov es, ax
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mov ss, ax
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xor ax, ax
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mov fs, ax
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mov gs, ax
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mov si, BufferStartLocation
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mov ebx, [si]
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mov si, ModeOffsetLocation
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mov eax, [si]
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mov si, CodeSegmentLocation
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mov edx, [si]
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mov di, ax
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sub di, 02h
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mov [di], dx
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sub di, 04h
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add eax, ebx
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mov [di],eax
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mov si, DataSegmentLocation
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mov edx, [si]
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mov si, GdtrLocation
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o32 lgdt [cs:si]
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mov si, IdtrLocation
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o32 lidt [cs:si]
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xor ax, ax
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mov ds, ax
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2016-07-29 15:08:01 +02:00
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mov eax, cr0 ; Get control register 0
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or eax, 000000003h ; Set PE bit (bit #0) & MP
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2016-07-20 16:44:39 +02:00
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mov cr0, eax
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jmp 0:strict dword 0 ; far jump to protected mode
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BITS 32
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Flat32Start: ; protected mode entry point
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mov ds, dx
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mov es, dx
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mov fs, dx
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mov gs, dx
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mov ss, dx
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mov esi, ebx
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2016-07-29 15:13:34 +02:00
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mov edi, esi
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add edi, EnableExecuteDisableLocation
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cmp byte [edi], 0
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jz SkipEnableExecuteDisable
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;
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; Enable IA32 PAE execute disable
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;
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mov ecx, 0xc0000080
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rdmsr
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bts eax, 11
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wrmsr
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mov edi, esi
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add edi, Cr3Location
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mov eax, dword [edi]
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mov cr3, eax
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mov eax, cr4
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bts eax, 5
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mov cr4, eax
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mov eax, cr0
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bts eax, 31
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mov cr0, eax
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SkipEnableExecuteDisable:
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2016-11-14 04:38:25 +01:00
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mov edi, esi
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add edi, InitFlagLocation
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cmp dword [edi], 1 ; 1 == ApInitConfig
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jnz GetApicId
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2016-07-29 15:13:34 +02:00
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2016-11-14 04:38:25 +01:00
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; AP init
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2016-07-20 16:44:39 +02:00
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mov edi, esi
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add edi, LockLocation
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mov eax, NotVacantFlag
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TestLock:
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xchg [edi], eax
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cmp eax, NotVacantFlag
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jz TestLock
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2016-11-14 04:38:25 +01:00
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mov ecx, esi
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add ecx, NumApsExecutingLocation
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inc dword [ecx]
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mov ebx, [ecx]
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Releaselock:
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mov eax, VacantFlag
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xchg [edi], eax
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2016-07-20 16:44:39 +02:00
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mov edi, esi
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add edi, StackSizeLocation
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mov eax, [edi]
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2016-11-14 04:38:25 +01:00
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mov ecx, ebx
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inc ecx
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mul ecx ; EAX = StackSize * (CpuNumber + 1)
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2016-07-20 16:44:39 +02:00
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mov edi, esi
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add edi, StackStartAddressLocation
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add eax, [edi]
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mov esp, eax
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2016-11-14 04:38:25 +01:00
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jmp CProcedureInvoke
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GetApicId:
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mov eax, 0
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cpuid
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cmp eax, 0bh
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UefiCpuPkg/MpInitLib: fix feature test for Extended Topology CPUID leaf
According to the Intel SDM (325462-060US / September 2016),
> INPUT EAX = 0BH: Returns Extended Topology Information
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> [...] Software must detect the presence of CPUID leaf 0BH by verifying
> (a) the highest leaf index supported by CPUID is >= 0BH, and
> (b) CPUID.0BH:EBX[15:0] reports a non-zero value. [...]
The "GetApicId" sections in the Ia32 and X64 "MpFuncs.nasm" files do not
perform check (b).
This causes an actual bug in the following OVMF setup:
- Intel W3550 host processor <http://ark.intel.com/products/39720/>,
- the QEMU/KVM guest's VCPU model is set to "host", that is, "the CPU
visible to the guest should be exactly the same as the host CPU".
Under "GetApicId", check (a) passes: the CPUID level of the W3550 is
exactly 11 decimal. However, leaf 11 itself is not supported, therefore
EDX is set to zero:
> If a value entered for CPUID.EAX is less than or equal to the maximum
> input value and the leaf is not supported on that processor then 0 is
> returned in all the registers.
Because we don't check (b), the "GetProcessorNumber" section of the code
is reached with an initial APIC ID of 0 in EDX on all of the APs. Given
that "GetProcessorNumber" searches the
"MP_CPU_EXCHANGE_INFO.CpuInfo[*].InitialApicId" fields for a match, all
APs enter ApWakeupFunction() with an identical "NumApsExecuting"
parameter. This results in unpredictable guest behavior (crashes, reboots,
hangs etc).
Reorganize the "GetApicId" section and add the missing check in both
assembly files.
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-22 13:58:54 +01:00
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jb NoX2Apic ; CPUID level below CPUID_EXTENDED_TOPOLOGY
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mov eax, 0bh
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xor ecx, ecx
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cpuid
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test ebx, 0ffffh
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jz NoX2Apic ; CPUID.0BH:EBX[15:0] is zero
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; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX
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jmp GetProcessorNumber
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NoX2Apic:
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2016-11-14 04:38:25 +01:00
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; Processor is not x2APIC capable, so get 8-bit APIC ID
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mov eax, 1
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cpuid
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shr ebx, 24
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mov edx, ebx
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GetProcessorNumber:
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;
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; Get processor number for this AP
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; Note that BSP may become an AP due to SwitchBsp()
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;
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xor ebx, ebx
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lea eax, [esi + CpuInfoLocation]
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mov edi, [eax]
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2016-07-20 16:44:39 +02:00
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2016-11-14 04:38:25 +01:00
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GetNextProcNumber:
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cmp [edi], edx ; APIC ID match?
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jz ProgramStack
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UefiCpuPkg/MpInitLib: support 64-bit AP stack addresses
The cached "CPU_INFO_IN_HOB.ApTopOfStack" field currently has type UINT32.
This is not ideal because the AP stacks are located within
"CpuMpData->Buffer", which is allocated with a plain AllocatePages() call
in MpInitLibInitialize():
platform CpuMpPei included PEI RAM > 4GB result
-------- ----------------- ------------- ------
Ia32 * n/a good
Ia32X64 no n/a BAD
Ia32X64 yes n/a good
X64 no * BAD
X64 yes no good
X64 yes yes BAD
- If we are on an Ia32X64 or X64 platform that does not include CpuMpPei,
then CpuDxe cannot reuse the CPU_INFO_IN_HOB structures preallocated by
CpuMpPei (through the CpuInitMpLib GUID HOB), and then AllocatePages()
-- invoked first in 64-bit DXE -- could return an address outside of
32-bit address space.
- If we are on an X64 platform where the permanent PEI RAM extends above
the 32-bit address space, then the same issue can surface even if
CpuMpPei is included: even the original allocation of the
CPU_INFO_IN_HOB structures, by CpuMpPei, could be satisfied from above
4GB.
The original "AP init" branch in "X64/MpFuncs.nasm" correctly considers a
64-bit stack start: the "MP_CPU_EXCHANGE_INFO.StackStart" field has type
UINTN, and the code uses QWORD addition and movement to set RSP from it.
Adapt the "GetApicId" branch of "X64/MpFuncs.nasm":
- change the type of "CPU_INFO_IN_HOB.ApTopOfStack" to UINT64,
- remove the explicit truncation to UINT32 in InitializeApData(),
- update the "GetNextProcNumber" iteration size to the new size of
"CPU_INFO_IN_HOB",
- set RSP with a QWORD movement from "CPU_INFO_IN_HOB.ApTopOfStack".
Because the same CPU_INFO_IN_HOB structure is used by "Ia32/MpFuncs.nasm",
we have to update the "GetNextProcNumber" iteration size there as well.
The ESP setting can be preserved as a DWORD movement from the original
offset (decimal 12), since our integers are little endian.
Cc: Jeff Fan <jeff.fan@intel.com>
Fixes: 845c5be1fd9bf7edfac4a103dfab70829686978f
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-16 23:31:11 +01:00
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add edi, 20
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2016-11-14 04:38:25 +01:00
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inc ebx
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jmp GetNextProcNumber
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2016-07-20 16:44:39 +02:00
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2016-11-14 04:38:25 +01:00
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ProgramStack:
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mov esp, [edi + 12]
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2016-07-20 16:44:39 +02:00
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CProcedureInvoke:
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push ebp ; push BIST data at top of AP stack
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xor ebp, ebp ; clear ebp for call stack trace
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push ebp
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mov ebp, esp
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mov eax, ASM_PFX(InitializeFloatingPointUnits)
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call eax ; Call assembly function to initialize FPU per UEFI spec
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push ebx ; Push NumApsExecuting
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mov eax, esi
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add eax, LockLocation
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push eax ; push address of exchange info data buffer
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mov edi, esi
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add edi, ApProcedureLocation
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mov eax, [edi]
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2016-07-29 15:08:01 +02:00
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call eax ; Invoke C function
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2016-07-20 16:44:39 +02:00
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2016-07-29 15:08:01 +02:00
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jmp $ ; Never reach here
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2016-07-20 16:44:39 +02:00
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RendezvousFunnelProcEnd:
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2016-07-20 16:47:47 +02:00
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;-------------------------------------------------------------------------------------
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2016-11-25 06:18:57 +01:00
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; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);
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2016-07-20 16:47:47 +02:00
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;-------------------------------------------------------------------------------------
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global ASM_PFX(AsmRelocateApLoop)
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ASM_PFX(AsmRelocateApLoop):
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AsmRelocateApLoopStart:
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2016-11-23 14:52:24 +01:00
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mov eax, esp
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mov esp, [eax + 16] ; TopOfApStack
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push dword [eax] ; push return address for stack trace
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push ebp
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mov ebp, esp
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mov ebx, [eax + 8] ; ApTargetCState
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mov ecx, [eax + 4] ; MwaitSupport
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2016-11-25 06:18:57 +01:00
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mov eax, [eax + 20] ; CountTofinish
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lock dec dword [eax] ; (*CountTofinish)--
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2016-11-23 14:52:24 +01:00
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cmp cl, 1 ; Check mwait-monitor support
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2016-07-20 16:47:47 +02:00
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jnz HltLoop
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MwaitLoop:
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mov eax, esp
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xor ecx, ecx
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xor edx, edx
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monitor
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2016-11-23 14:52:24 +01:00
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mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]
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2016-07-20 16:47:47 +02:00
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shl eax, 4
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mwait
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jmp MwaitLoop
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HltLoop:
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cli
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hlt
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jmp HltLoop
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AsmRelocateApLoopEnd:
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2016-07-20 16:44:39 +02:00
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;-------------------------------------------------------------------------------------
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; AsmGetAddressMap (&AddressMap);
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;-------------------------------------------------------------------------------------
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global ASM_PFX(AsmGetAddressMap)
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ASM_PFX(AsmGetAddressMap):
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pushad
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mov ebp,esp
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mov ebx, [ebp + 24h]
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mov dword [ebx], RendezvousFunnelProcStart
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mov dword [ebx + 4h], Flat32Start - RendezvousFunnelProcStart
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mov dword [ebx + 8h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
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2016-07-20 16:56:09 +02:00
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mov dword [ebx + 0Ch], AsmRelocateApLoopStart
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mov dword [ebx + 10h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart
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2016-07-20 16:44:39 +02:00
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popad
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ret
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;-------------------------------------------------------------------------------------
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;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
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;about to become an AP. It switches it'stack with the current AP.
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;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);
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;-------------------------------------------------------------------------------------
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global ASM_PFX(AsmExchangeRole)
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ASM_PFX(AsmExchangeRole):
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; DO NOT call other functions in this function, since 2 CPU may use 1 stack
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; at the same time. If 1 CPU try to call a function, stack will be corrupted.
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pushad
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mov ebp,esp
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; esi contains MyInfo pointer
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mov esi, [ebp + 24h]
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; edi contains OthersInfo pointer
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mov edi, [ebp + 28h]
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;Store EFLAGS, GDTR and IDTR register to stack
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pushfd
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mov eax, cr4
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push eax ; push cr4 firstly
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mov eax, cr0
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push eax
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sgdt [esi + 8]
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sidt [esi + 14]
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; Store the its StackPointer
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mov [esi + 4],esp
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; update its switch state to STORED
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mov byte [esi], CPU_SWITCH_STATE_STORED
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WaitForOtherStored:
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; wait until the other CPU finish storing its state
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cmp byte [edi], CPU_SWITCH_STATE_STORED
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jz OtherStored
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pause
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jmp WaitForOtherStored
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OtherStored:
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; Since another CPU already stored its state, load them
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; load GDTR value
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lgdt [edi + 8]
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; load IDTR value
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lidt [edi + 14]
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; load its future StackPointer
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|
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mov esp, [edi + 4]
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; update the other CPU's switch state to LOADED
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mov byte [edi], CPU_SWITCH_STATE_LOADED
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WaitForOtherLoaded:
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; wait until the other CPU finish loading new state,
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|
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; otherwise the data in stack may corrupt
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|
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cmp byte [esi], CPU_SWITCH_STATE_LOADED
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|
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jz OtherLoaded
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pause
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jmp WaitForOtherLoaded
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OtherLoaded:
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|
|
; since the other CPU already get the data it want, leave this procedure
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pop eax
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mov cr0, eax
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pop eax
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mov cr4, eax
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popfd
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|
popad
|
|
|
|
ret
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