audk/OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c

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/** @file
Reset System Library functions for OVMF
Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/TimerLib.h>
VOID
AcpiPmControl (
UINTN SuspendType
)
{
ASSERT (SuspendType < 6);
IoBitFieldWrite16 (PcdGet16 (PcdAcpiPmBaseAddress) + 4, 10, 13, (UINT16) SuspendType);
IoOr16 (PcdGet16 (PcdAcpiPmBaseAddress) + 4, BIT13);
CpuDeadLoop ();
}
/**
Calling this function causes a system-wide reset. This sets
all circuitry within the system to its initial state. This type of reset
is asynchronous to system operation and operates without regard to
cycle boundaries.
System reset should not return, if it returns, it means the system does
not support cold reset.
**/
VOID
EFIAPI
ResetCold (
VOID
)
{
OvmfPkg: attempt to trigger cold reset through PIIX3 reset control register The reset requested via the keyboard controller (port 0x64) is actually a soft reset, but qemu has supported it since forever (plus qemu has not distinguished between hard reset and soft reset, although this is changing now). Therefore leave the current IoWrite() in place for compatibility. On qemu versions with commit 1ec4ba74 ("PIIX3: reset the VM when the Reset Control Register's RCPU bit gets set"), use the PIIX3 RCR as first choice. In the future qemu will act differently on soft vs. hard reset requests, and we should honor that in ResetCold(). Writing to ioport 0xCF9 on qemu builds prior to commit 1ec4ba74 should have no effect. Access to the PCI host config register went through several implementations in qemu. Commit 9f6f0423 ("pci_host: rewrite using rwhandler") seems safe, both before and after. Commit d0ed8076 ("pci_host: convert conf index and data ports to memory API") inadvertently dropped the alignment/size check, causing a boot regression on NetBSD. It was fixed about six months later in commit cdde6ffc, which is current. Translating that to qemu releases, the bug was visible from v1.0 to v1.1.0. On physical hardware cycling between reset methods is sometimes necessary <http://mjg59.dreamwidth.org/3561.html>. On qemu the port access should trap immediately. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14157 6f19259b-4bc3-4df7-8a09-765794883524
2013-03-04 18:38:24 +01:00
IoWrite8 (0xCF9, BIT2 | BIT1); // 1st choice: PIIX3 RCR, RCPU|SRST
MicroSecondDelay (50);
OvmfPkg: attempt to trigger cold reset through PIIX3 reset control register The reset requested via the keyboard controller (port 0x64) is actually a soft reset, but qemu has supported it since forever (plus qemu has not distinguished between hard reset and soft reset, although this is changing now). Therefore leave the current IoWrite() in place for compatibility. On qemu versions with commit 1ec4ba74 ("PIIX3: reset the VM when the Reset Control Register's RCPU bit gets set"), use the PIIX3 RCR as first choice. In the future qemu will act differently on soft vs. hard reset requests, and we should honor that in ResetCold(). Writing to ioport 0xCF9 on qemu builds prior to commit 1ec4ba74 should have no effect. Access to the PCI host config register went through several implementations in qemu. Commit 9f6f0423 ("pci_host: rewrite using rwhandler") seems safe, both before and after. Commit d0ed8076 ("pci_host: convert conf index and data ports to memory API") inadvertently dropped the alignment/size check, causing a boot regression on NetBSD. It was fixed about six months later in commit cdde6ffc, which is current. Translating that to qemu releases, the bug was visible from v1.0 to v1.1.0. On physical hardware cycling between reset methods is sometimes necessary <http://mjg59.dreamwidth.org/3561.html>. On qemu the port access should trap immediately. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14157 6f19259b-4bc3-4df7-8a09-765794883524
2013-03-04 18:38:24 +01:00
IoWrite8 (0x64, 0xfe); // 2nd choice: keyboard controller
CpuDeadLoop ();
}
/**
Calling this function causes a system-wide initialization. The processors
are set to their initial state, and pending cycles are not corrupted.
System reset should not return, if it returns, it means the system does
not support warm reset.
**/
VOID
EFIAPI
ResetWarm (
VOID
)
{
IoWrite8 (0x64, 0xfe);
CpuDeadLoop ();
}
/**
Calling this function causes the system to enter a power state equivalent
to the ACPI G2/S5 or G3 states.
System shutdown should not return, if it returns, it means the system does
not support shut down reset.
**/
VOID
EFIAPI
ResetShutdown (
VOID
)
{
AcpiPmControl (0);
ASSERT (FALSE);
}
/**
Calling this function causes the system to enter a power state for capsule
update.
Reset update should not return, if it returns, it means the system does
not support capsule update.
**/
VOID
EFIAPI
EnterS3WithImmediateWake (
VOID
)
{
AcpiPmControl (1);
ASSERT (FALSE);
}