OvmfPkg: attempt to trigger cold reset through PIIX3 reset control register

The reset requested via the keyboard controller (port 0x64) is actually a
soft reset, but qemu has supported it since forever (plus qemu has not
distinguished between hard reset and soft reset, although this is changing
now). Therefore leave the current IoWrite() in place for compatibility.

On qemu versions with commit 1ec4ba74 ("PIIX3: reset the VM when the Reset
Control Register's RCPU bit gets set"), use the PIIX3 RCR as first choice.
In the future qemu will act differently on soft vs. hard reset requests,
and we should honor that in ResetCold().

  Writing to ioport 0xCF9 on qemu builds prior to commit 1ec4ba74 should
  have no effect. Access to the PCI host config register went through
  several implementations in qemu. Commit 9f6f0423 ("pci_host: rewrite
  using rwhandler") seems safe, both before and after.

  Commit d0ed8076 ("pci_host: convert conf index and data ports to memory
  API") inadvertently dropped the alignment/size check, causing a boot
  regression on NetBSD. It was fixed about six months later in commit
  cdde6ffc, which is current. Translating that to qemu releases, the bug
  was visible from v1.0 to v1.1.0.

On physical hardware cycling between reset methods is sometimes necessary
<http://mjg59.dreamwidth.org/3561.html>. On qemu the port access should
trap immediately.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14157 6f19259b-4bc3-4df7-8a09-765794883524

OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c

@@ -45,7 +45,8 @@ ResetCold (
   VOID
   )
 {
-  IoWrite8 (0x64, 0xfe);
+  IoWrite8 (0xCF9, BIT2 | BIT1); // 1st choice: PIIX3 RCR, RCPU|SRST
+  IoWrite8 (0x64, 0xfe);         // 2nd choice: keyboard controller
 }
 
 /**