mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: Use macro CR4_CET_BIT to replace hard code value in Cet.nasm.
Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Cc: Tan Dun <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
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@ -1,10 +1,11 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;-------------------------------------------------------------------------------
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%include "Nasm.inc"
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%include "Cet.inc"
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SECTION .text
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@ -16,7 +17,7 @@ ASM_PFX(DisableCet):
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incsspd eax
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mov eax, cr4
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btr eax, 23 ; clear CET
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btr eax, CR4_CET_BIT ; clear CET
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mov cr4, eax
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ret
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@ -24,7 +25,7 @@ global ASM_PFX(EnableCet)
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ASM_PFX(EnableCet):
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mov eax, cr4
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bts eax, 23 ; set CET
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bts eax, CR4_CET_BIT ; set CET
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mov cr4, eax
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; use jmp to skip the check for ret
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@ -1,10 +1,11 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;-------------------------------------------------------------------------------
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%include "Nasm.inc"
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%include "Cet.inc"
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DEFAULT REL
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SECTION .text
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@ -17,7 +18,7 @@ ASM_PFX(DisableCet):
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incsspq rax
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mov rax, cr4
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btr eax, 23 ; clear CET
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btr eax, CR4_CET_BIT ; clear CET
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mov cr4, rax
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ret
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@ -25,7 +26,7 @@ global ASM_PFX(EnableCet)
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ASM_PFX(EnableCet):
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mov rax, cr4
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bts eax, 23 ; set CET
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bts eax, CR4_CET_BIT ; set CET
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mov cr4, rax
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; use jmp to skip the check for ret
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