mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/PL011Uart: Allowed to change UART settings in its initialization function
Because this driver can be used for different purposes (Terminal, Debug port, communication), its initialization function has been extended to accept additional settings. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13071 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
b0855f925c
commit
051e63bb55
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@ -101,8 +101,9 @@
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
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## PL011 UART
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gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F
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gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020
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gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
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gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
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gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
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## PL031 RealTimeClock
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gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
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@ -1,137 +1,361 @@
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/** @file
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Serial I/O Port library functions with no library constructor/destructor
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Include/Uefi.h>
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#include <Library/IoLib.h>
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#include <Drivers/PL011Uart.h>
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/*
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Programmed hardware of Serial port.
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@return Always return EFI_UNSUPPORTED.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartInitialize (
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IN UINTN UartBase,
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IN UINTN BaudRate,
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IN UINTN LineControl
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)
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{
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if (BaudRate == 115200) {
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// Initialize baud rate generator
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MmioWrite32 (UartBase + UARTIBRD, UART_115200_IDIV);
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MmioWrite32 (UartBase + UARTFBRD, UART_115200_FDIV);
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} else if (BaudRate == 38400) {
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// Initialize baud rate generator
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MmioWrite32 (UartBase + UARTIBRD, UART_38400_IDIV);
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MmioWrite32 (UartBase + UARTFBRD, UART_38400_FDIV);
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} else if (BaudRate == 19200) {
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// Initialize baud rate generator
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MmioWrite32 (UartBase + UARTIBRD, UART_19200_IDIV);
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MmioWrite32 (UartBase + UARTFBRD, UART_19200_FDIV);
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} else {
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return EFI_INVALID_PARAMETER;
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}
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// No parity, 1 stop, no fifo, 8 data bits
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MmioWrite32 (UartBase + UARTLCR_H, LineControl);
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// Clear any pending errors
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MmioWrite32 (UartBase + UARTECR, 0);
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// Enable tx, rx, and uart overall
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MmioWrite32 (UartBase + UARTCR, PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
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return EFI_SUCCESS;
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}
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/**
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Write data to serial device.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Write data failed.
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@retval !0 Actual number of bytes written to serial device.
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**/
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UINTN
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EFIAPI
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PL011UartWrite (
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IN UINTN UartBase,
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IN UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINTN Count;
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for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
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while ((MmioRead32 (UartBase + UARTFR) & UART_TX_EMPTY_FLAG_MASK) == 0);
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MmioWrite8 (UartBase + UARTDR, *Buffer);
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}
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return NumberOfBytes;
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}
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/**
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Read data from serial device and save the data in buffer.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Read data failed.
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@retval !0 Actual number of bytes read from serial device.
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**/
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UINTN
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EFIAPI
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PL011UartRead (
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IN UINTN UartBase,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINTN Count;
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for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
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while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
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*Buffer = MmioRead8 (UartBase + UARTDR);
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}
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return NumberOfBytes;
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}
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/**
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Check to see if any data is available to be read from the debug device.
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@retval EFI_SUCCESS At least one byte of data is available to be read
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@retval EFI_NOT_READY No data is available to be read
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@retval EFI_DEVICE_ERROR The serial device is not functioning properly
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**/
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BOOLEAN
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EFIAPI
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PL011UartPoll (
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IN UINTN UartBase
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)
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{
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return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
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}
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/** @file
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Serial I/O Port library functions with no library constructor/destructor
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/PL011Uart.h>
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/*
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Initialise the serial port to the specified settings.
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All unspecified settings will be set to the default values.
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@return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartInitializePort (
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IN UINTN UartBase,
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IN UINT64 BaudRate,
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IN UINT32 ReceiveFifoDepth,
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IN UINT32 Timeout,
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IN EFI_PARITY_TYPE Parity,
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IN UINT8 DataBits,
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IN EFI_STOP_BITS_TYPE StopBits
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)
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{
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UINT32 LineControl;
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UINT32 Divisor;
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// The BaudRate must be passed
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if (BaudRate == 0) {
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return RETURN_INVALID_PARAMETER;
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}
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LineControl = 0;
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// The PL011 supports a buffer of either 1 or 32 chars. Therefore we can accept
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// 1 char buffer as the minimum fifo size. Because everything can be rounded down,
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// there is no maximum fifo size.
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if (ReceiveFifoDepth == 0) {
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LineControl |= PL011_UARTLCR_H_FEN;
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} else if (ReceiveFifoDepth < 32) {
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// Nothing else to do. 1 byte fifo is default.
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} else if (ReceiveFifoDepth >= 32) {
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LineControl |= PL011_UARTLCR_H_FEN;
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}
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//
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// Parity
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//
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switch (Parity) {
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case DefaultParity:
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case NoParity:
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// Nothing to do. Parity is disabled by default.
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break;
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case EvenParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
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break;
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case OddParity:
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LineControl |= PL011_UARTLCR_H_PEN;
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break;
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case MarkParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS | PL011_UARTLCR_H_EPS);
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break;
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case SpaceParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Data Bits
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//
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switch (DataBits) {
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case 0:
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case 8:
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LineControl |= PL011_UARTLCR_H_WLEN_8;
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break;
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case 7:
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LineControl |= PL011_UARTLCR_H_WLEN_7;
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break;
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case 6:
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LineControl |= PL011_UARTLCR_H_WLEN_6;
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break;
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case 5:
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LineControl |= PL011_UARTLCR_H_WLEN_5;
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Stop Bits
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//
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switch (StopBits) {
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case DefaultStopBits:
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case OneStopBit:
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// Nothing to do. One stop bit is enabled by default.
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break;
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case TwoStopBits:
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LineControl |= PL011_UARTLCR_H_STP2;
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break;
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case OneFiveStopBits:
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// Only 1 or 2 stops bits are supported
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default:
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return RETURN_INVALID_PARAMETER;
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}
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// Don't send the LineControl value to the PL011 yet,
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// wait until after the Baud Rate setting.
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// This ensures we do not mess up the UART settings halfway through
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// in the rare case when there is an error with the Baud Rate.
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//
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// Baud Rate
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//
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if (PcdGet32(PL011UartInteger) != 0) {
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// Integer and Factional part must be different of 0
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ASSERT(PcdGet32(PL011UartFractional) != 0);
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MmioWrite32 (UartBase + UARTIBRD, PcdGet32(PL011UartInteger));
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MmioWrite32 (UartBase + UARTFBRD, PcdGet32(PL011UartFractional));
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} else {
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Divisor = (PcdGet32 (PL011UartClkInHz) * 4) / BaudRate;
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MmioWrite32 (UartBase + UARTIBRD, Divisor >> 6);
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MmioWrite32 (UartBase + UARTFBRD, Divisor & 0x3F);
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}
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// No parity, 1 stop, no fifo, 8 data bits
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MmioWrite32 (UartBase + UARTLCR_H, LineControl);
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// Clear any pending errors
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MmioWrite32 (UartBase + UARTECR, 0);
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// Enable tx, rx, and uart overall
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MmioWrite32 (UartBase + UARTCR, PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
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return RETURN_SUCCESS;
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}
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/**
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Set the serial device control bits.
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@param UartBase The base address of the PL011 UART.
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@param Control Control bits which are to be set on the serial device.
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@retval EFI_SUCCESS The new control bits were set on the serial device.
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@retval EFI_UNSUPPORTED The serial device does not support this operation.
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@retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartSetControl (
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IN UINTN UartBase,
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IN UINT32 Control
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)
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{
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UINT32 Bits;
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UINT32 ValidControlBits;
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ValidControlBits = ( EFI_SERIAL_REQUEST_TO_SEND
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| EFI_SERIAL_DATA_TERMINAL_READY
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// | EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE // Not implemented yet.
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// | EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE // Not implemented yet.
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| EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
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);
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if (Control & (~ValidControlBits)) {
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return EFI_UNSUPPORTED;
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}
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Bits = MmioRead32 (UartBase + UARTCR);
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if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
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Bits |= PL011_UARTCR_RTS;
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}
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if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {
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Bits |= PL011_UARTCR_DTR;
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}
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if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
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Bits |= PL011_UARTCR_LBE;
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}
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if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
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Bits |= (PL011_UARTCR_CTSEN & PL011_UARTCR_RTSEN);
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}
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MmioWrite32 (UartBase + UARTCR, Bits);
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return RETURN_SUCCESS;
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}
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/**
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Get the serial device control bits.
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@param UartBase The base address of the PL011 UART.
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@param Control Control signals read from the serial device.
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@retval EFI_SUCCESS The control bits were read from the serial device.
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@retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartGetControl (
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IN UINTN UartBase,
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OUT UINT32 *Control
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)
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{
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UINT32 FlagRegister;
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UINT32 ControlRegister;
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FlagRegister = MmioRead32 (UartBase + UARTFR);
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ControlRegister = MmioRead32 (UartBase + UARTCR);
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*Control = 0;
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if ((FlagRegister & PL011_UARTFR_CTS) == PL011_UARTFR_CTS) {
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*Control |= EFI_SERIAL_CLEAR_TO_SEND;
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}
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if ((FlagRegister & PL011_UARTFR_DSR) == PL011_UARTFR_DSR) {
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*Control |= EFI_SERIAL_DATA_SET_READY;
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}
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if ((FlagRegister & PL011_UARTFR_RI) == PL011_UARTFR_RI) {
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*Control |= EFI_SERIAL_RING_INDICATE;
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}
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if ((FlagRegister & PL011_UARTFR_DCD) == PL011_UARTFR_DCD) {
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*Control |= EFI_SERIAL_CARRIER_DETECT;
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}
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if ((ControlRegister & PL011_UARTCR_RTS) == PL011_UARTCR_RTS) {
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*Control |= EFI_SERIAL_REQUEST_TO_SEND;
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}
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if ((ControlRegister & PL011_UARTCR_DTR) == PL011_UARTCR_DTR) {
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*Control |= EFI_SERIAL_DATA_TERMINAL_READY;
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}
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if ((FlagRegister & PL011_UARTFR_RXFE) == PL011_UARTFR_RXFE) {
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*Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
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}
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if ((FlagRegister & PL011_UARTFR_TXFE) == PL011_UARTFR_TXFE) {
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*Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
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}
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if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {
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*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
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}
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#ifdef NEVER
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// ToDo: Implement EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE
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if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {
|
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*Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
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}
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// ToDo: Implement EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE
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if (SoftwareLoopbackEnable) {
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*Control |= EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
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}
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#endif
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return RETURN_SUCCESS;
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}
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/**
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Write data to serial device.
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|
||||
@param Buffer Point of data buffer which need to be written.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
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@retval 0 Write data failed.
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@retval !0 Actual number of bytes written to serial device.
|
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|
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**/
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UINTN
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EFIAPI
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PL011UartWrite (
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IN UINTN UartBase,
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IN UINT8 *Buffer,
|
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IN UINTN NumberOfBytes
|
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)
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{
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UINTN Count;
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|
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for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
|
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while ((MmioRead32 (UartBase + UARTFR) & UART_TX_EMPTY_FLAG_MASK) == 0);
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MmioWrite8 (UartBase + UARTDR, *Buffer);
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}
|
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|
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return NumberOfBytes;
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}
|
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|
||||
/**
|
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Read data from serial device and save the data in buffer.
|
||||
|
||||
@param Buffer Point of data buffer which need to be written.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Read data failed.
|
||||
@retval !0 Actual number of bytes read from serial device.
|
||||
|
||||
**/
|
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UINTN
|
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EFIAPI
|
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PL011UartRead (
|
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IN UINTN UartBase,
|
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OUT UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
)
|
||||
{
|
||||
UINTN Count;
|
||||
|
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for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
|
||||
while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
|
||||
*Buffer = MmioRead8 (UartBase + UARTDR);
|
||||
}
|
||||
|
||||
return NumberOfBytes;
|
||||
}
|
||||
|
||||
/**
|
||||
Check to see if any data is available to be read from the debug device.
|
||||
|
||||
@retval EFI_SUCCESS At least one byte of data is available to be read
|
||||
@retval EFI_NOT_READY No data is available to be read
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
PL011UartPoll (
|
||||
IN UINTN UartBase
|
||||
)
|
||||
{
|
||||
return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,36 +1,39 @@
|
|||
#/** @file
|
||||
#
|
||||
# Component description file for PL011Uart module
|
||||
#
|
||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = PL011Uart
|
||||
FILE_GUID = 4ec8b120-8307-11e0-bc91-0002a5d5c51b
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = PL011UartLib
|
||||
|
||||
[Sources.common]
|
||||
PL011Uart.c
|
||||
|
||||
[LibraryClasses]
|
||||
IoLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
# MdeModulePkg/MdeModulePkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[Pcd]
|
||||
#/** @file
|
||||
#
|
||||
# Component description file for PL011Uart module
|
||||
#
|
||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = PL011Uart
|
||||
FILE_GUID = 4ec8b120-8307-11e0-bc91-0002a5d5c51b
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = PL011UartLib
|
||||
|
||||
[Sources.common]
|
||||
PL011Uart.c
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
IoLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[Pcd]
|
||||
gArmPlatformTokenSpaceGuid.PL011UartClkInHz
|
||||
gArmPlatformTokenSpaceGuid.PL011UartInteger
|
||||
gArmPlatformTokenSpaceGuid.PL011UartFractional
|
||||
|
|
|
|||
|
|
@ -1,141 +1,188 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __PL011_UART_H__
|
||||
#define __PL011_UART_H__
|
||||
|
||||
// PL011 Registers
|
||||
#define UARTDR 0x000
|
||||
#define UARTRSR 0x004
|
||||
#define UARTECR 0x004
|
||||
#define UARTFR 0x018
|
||||
#define UARTILPR 0x020
|
||||
#define UARTIBRD 0x024
|
||||
#define UARTFBRD 0x028
|
||||
#define UARTLCR_H 0x02C
|
||||
#define UARTCR 0x030
|
||||
#define UARTIFLS 0x034
|
||||
#define UARTIMSC 0x038
|
||||
#define UARTRIS 0x03C
|
||||
#define UARTMIS 0x040
|
||||
#define UARTICR 0x044
|
||||
#define UARTDMACR 0x048
|
||||
|
||||
#define UART_115200_IDIV 13 // Integer Part
|
||||
#define UART_115200_FDIV 1 // Fractional Part
|
||||
#define UART_38400_IDIV 39
|
||||
#define UART_38400_FDIV 5
|
||||
#define UART_19200_IDIV 12
|
||||
#define UART_19200_FDIV 37
|
||||
|
||||
// Data status bits
|
||||
#define UART_DATA_ERROR_MASK 0x0F00
|
||||
|
||||
// Status reg bits
|
||||
#define UART_STATUS_ERROR_MASK 0x0F
|
||||
|
||||
// Flag reg bits
|
||||
#define UART_TX_EMPTY_FLAG_MASK 0x80
|
||||
#define UART_RX_FULL_FLAG_MASK 0x40
|
||||
#define UART_TX_FULL_FLAG_MASK 0x20
|
||||
#define UART_RX_EMPTY_FLAG_MASK 0x10
|
||||
#define UART_BUSY_FLAG_MASK 0x08
|
||||
|
||||
// Control reg bits
|
||||
#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
|
||||
#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
|
||||
#define PL011_UARTCR_RTS (1 << 11) // Request to send
|
||||
#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
|
||||
#define PL011_UARTCR_RXE (1 << 9) // Receive enable
|
||||
#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
|
||||
#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
|
||||
|
||||
// Line Control Register Bits
|
||||
#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
|
||||
#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
|
||||
#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
|
||||
#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
|
||||
#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
|
||||
#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
|
||||
#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
|
||||
#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
|
||||
#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
|
||||
#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
|
||||
|
||||
/*
|
||||
|
||||
Programmed hardware of Serial port.
|
||||
|
||||
@return Always return EFI_UNSUPPORTED.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
PL011UartInitialize (
|
||||
IN UINTN UartBase,
|
||||
IN UINTN BaudRate,
|
||||
IN UINTN LineControl
|
||||
);
|
||||
|
||||
/**
|
||||
Write data to serial device.
|
||||
|
||||
@param Buffer Point of data buffer which need to be writed.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Write data failed.
|
||||
@retval !0 Actual number of bytes writed to serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL011UartWrite (
|
||||
IN UINTN UartBase,
|
||||
IN UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
);
|
||||
|
||||
/**
|
||||
Read data from serial device and save the datas in buffer.
|
||||
|
||||
@param Buffer Point of data buffer which need to be writed.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Read data failed.
|
||||
@retval !0 Aactual number of bytes read from serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL011UartRead (
|
||||
IN UINTN UartBase,
|
||||
OUT UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
);
|
||||
|
||||
/**
|
||||
Check to see if any data is avaiable to be read from the debug device.
|
||||
|
||||
@retval EFI_SUCCESS At least one byte of data is avaiable to be read
|
||||
@retval EFI_NOT_READY No data is avaiable to be read
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
PL011UartPoll (
|
||||
IN UINTN UartBase
|
||||
);
|
||||
|
||||
#endif
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __PL011_UART_H__
|
||||
#define __PL011_UART_H__
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Protocol/SerialIo.h>
|
||||
|
||||
// PL011 Registers
|
||||
#define UARTDR 0x000
|
||||
#define UARTRSR 0x004
|
||||
#define UARTECR 0x004
|
||||
#define UARTFR 0x018
|
||||
#define UARTILPR 0x020
|
||||
#define UARTIBRD 0x024
|
||||
#define UARTFBRD 0x028
|
||||
#define UARTLCR_H 0x02C
|
||||
#define UARTCR 0x030
|
||||
#define UARTIFLS 0x034
|
||||
#define UARTIMSC 0x038
|
||||
#define UARTRIS 0x03C
|
||||
#define UARTMIS 0x040
|
||||
#define UARTICR 0x044
|
||||
#define UARTDMACR 0x048
|
||||
|
||||
// Data status bits
|
||||
#define UART_DATA_ERROR_MASK 0x0F00
|
||||
|
||||
// Status reg bits
|
||||
#define UART_STATUS_ERROR_MASK 0x0F
|
||||
|
||||
// Flag reg bits
|
||||
#define PL011_UARTFR_RI (1 << 8) // Ring indicator
|
||||
#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
|
||||
#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
|
||||
#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
|
||||
#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
|
||||
#define PL011_UARTFR_BUSY (1 << 3) // UART busy
|
||||
#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
|
||||
#define PL011_UARTFR_DSR (1 << 1) // Data set ready
|
||||
#define PL011_UARTFR_CTS (1 << 0) // Clear to send
|
||||
|
||||
// Flag reg bits - alternative names
|
||||
#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
|
||||
#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
|
||||
#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
|
||||
#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
|
||||
#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
|
||||
|
||||
// Control reg bits
|
||||
#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
|
||||
#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
|
||||
#define PL011_UARTCR_RTS (1 << 11) // Request to send
|
||||
#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
|
||||
#define PL011_UARTCR_RXE (1 << 9) // Receive enable
|
||||
#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
|
||||
#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
|
||||
#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
|
||||
|
||||
// Line Control Register Bits
|
||||
#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
|
||||
#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
|
||||
#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
|
||||
#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
|
||||
#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
|
||||
#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
|
||||
#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
|
||||
#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
|
||||
#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
|
||||
#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
|
||||
|
||||
/*
|
||||
|
||||
Programmed hardware of Serial port.
|
||||
|
||||
@return Always return EFI_UNSUPPORTED.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
PL011UartInitializePort (
|
||||
IN UINTN UartBase,
|
||||
IN UINT64 BaudRate,
|
||||
IN UINT32 ReceiveFifoDepth,
|
||||
IN UINT32 Timeout,
|
||||
IN EFI_PARITY_TYPE Parity,
|
||||
IN UINT8 DataBits,
|
||||
IN EFI_STOP_BITS_TYPE StopBits
|
||||
);
|
||||
|
||||
/**
|
||||
Set the serial device control bits.
|
||||
|
||||
@param UartBase The base address of the PL011 UART.
|
||||
@param Control Control bits which are to be set on the serial device.
|
||||
|
||||
@retval EFI_SUCCESS The new control bits were set on the serial device.
|
||||
@retval EFI_UNSUPPORTED The serial device does not support this operation.
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
PL011UartSetControl (
|
||||
IN UINTN UartBase,
|
||||
IN UINT32 Control
|
||||
);
|
||||
|
||||
/**
|
||||
Get the serial device control bits.
|
||||
|
||||
@param UartBase The base address of the PL011 UART.
|
||||
@param Control Control signals read from the serial device.
|
||||
|
||||
@retval EFI_SUCCESS The control bits were read from the serial device.
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
PL011UartGetControl (
|
||||
IN UINTN UartBase,
|
||||
OUT UINT32 *Control
|
||||
);
|
||||
|
||||
/**
|
||||
Write data to serial device.
|
||||
|
||||
@param Buffer Point of data buffer which need to be written.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Write data failed.
|
||||
@retval !0 Actual number of bytes written to serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL011UartWrite (
|
||||
IN UINTN UartBase,
|
||||
IN UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
);
|
||||
|
||||
/**
|
||||
Read data from serial device and save the data in buffer.
|
||||
|
||||
@param Buffer Point of data buffer which need to be written.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Read data failed.
|
||||
@retval !0 Actual number of bytes read from serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL011UartRead (
|
||||
IN UINTN UartBase,
|
||||
OUT UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
);
|
||||
|
||||
/**
|
||||
Check to see if any data is available to be read from the debug device.
|
||||
|
||||
@retval EFI_SUCCESS At least one byte of data is available to be read
|
||||
@retval EFI_NOT_READY No data is available to be read
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
PL011UartPoll (
|
||||
IN UINTN UartBase
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/** @file
|
||||
Serial I/O Port library functions with no library constructor/destructor
|
||||
|
||||
|
||||
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||
Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
**/
|
||||
|
||||
#include <Include/Uefi.h>
|
||||
#include <Include/Base.h>
|
||||
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
|
||||
Programmed hardware of Serial port.
|
||||
|
||||
@return Always return EFI_UNSUPPORTED.
|
||||
@return Always return RETURN_UNSUPPORTED.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
|
|
@ -36,21 +36,24 @@ SerialPortInitialize (
|
|||
VOID
|
||||
)
|
||||
{
|
||||
// No parity, 1 stop, no fifo, 8 data bits
|
||||
return PL011UartInitialize (
|
||||
return PL011UartInitializePort (
|
||||
(UINTN)PcdGet64 (PcdSerialRegisterBase),
|
||||
(UINTN)PcdGet64 (PcdUartDefaultBaudRate),
|
||||
PL011_UARTLCR_H_WLEN_8);
|
||||
0, // Use the default value for Fifo depth
|
||||
0, // Use the default value for Timeout,
|
||||
(EFI_PARITY_TYPE)PcdGet8 (PcdUartDefaultParity),
|
||||
PcdGet8 (PcdUartDefaultDataBits),
|
||||
(EFI_STOP_BITS_TYPE) PcdGet8 (PcdUartDefaultStopBits));
|
||||
}
|
||||
|
||||
/**
|
||||
Write data to serial device.
|
||||
|
||||
@param Buffer Point of data buffer which need to be writed.
|
||||
@param Buffer Point of data buffer which need to be written.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Write data failed.
|
||||
@retval !0 Actual number of bytes writed to serial device.
|
||||
@retval !0 Actual number of bytes written to serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
|
|
@ -64,13 +67,13 @@ SerialPortWrite (
|
|||
}
|
||||
|
||||
/**
|
||||
Read data from serial device and save the datas in buffer.
|
||||
Read data from serial device and save the data in buffer.
|
||||
|
||||
@param Buffer Point of data buffer which need to be writed.
|
||||
@param Buffer Point of data buffer which need to be written.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Read data failed.
|
||||
@retval !0 Aactual number of bytes read from serial device.
|
||||
@retval !0 Actual number of bytes read from serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
|
|
@ -84,10 +87,10 @@ SerialPortRead (
|
|||
}
|
||||
|
||||
/**
|
||||
Check to see if any data is avaiable to be read from the debug device.
|
||||
Check to see if any data is available to be read from the debug device.
|
||||
|
||||
@retval EFI_SUCCESS At least one byte of data is avaiable to be read
|
||||
@retval EFI_NOT_READY No data is avaiable to be read
|
||||
@retval EFI_SUCCESS At least one byte of data is available to be read
|
||||
@retval EFI_NOT_READY No data is available to be read
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
|
||||
|
||||
**/
|
||||
|
|
|
|||
|
|
@ -1,38 +1,42 @@
|
|||
#/** @file
|
||||
#
|
||||
# Component discription file for NorFlashDxe module
|
||||
#
|
||||
# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = PL011SerialPortLib
|
||||
FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = SerialPortLib
|
||||
|
||||
[Sources.common]
|
||||
PL011SerialPortLib.c
|
||||
|
||||
[LibraryClasses]
|
||||
PL011UartLib
|
||||
PcdLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[Pcd]
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
|
||||
#/** @file
|
||||
#
|
||||
# Component description file for PL011SerialPortLib module
|
||||
#
|
||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = PL011SerialPortLib
|
||||
FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = SerialPortLib
|
||||
|
||||
[Sources.common]
|
||||
PL011SerialPortLib.c
|
||||
|
||||
[LibraryClasses]
|
||||
PL011UartLib
|
||||
PcdLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[Pcd]
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
|
||||
|
|
|
|||
Loading…
Reference in New Issue