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ArmPkg/CpuDxe/AArch64/ExceptionSupport.S: Fix immediate syntax 

GNU as assembles instructions without the '#' before immediates. Clang doesn't.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15507 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Brendan Jackman 2014-05-08 14:56:42 +00:00 committed by oliviermartin
parent 919a3a026c
commit 0db208eaca
1 changed files with 13 additions and 13 deletions
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26
ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
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@ -1,5 +1,5 @@
//
// Copyright (c) 2011 - 2013 ARM LTD. All rights reserved.<BR>
// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR>
// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
@ -130,7 +130,7 @@ GCC_ASM_EXPORT(CommonCExceptionHandler)
// In order to save the SP we need to put it somwhere else first.
// STR only works with XZR/WZR directly
#define SAVE_SP \
add x1, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE; \
add x1, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE); \
REG_ONE (x1, 0x0f8, GP_CONTEXT_SIZE);
#define ALL_FP_REGS \
@ -246,7 +246,7 @@ ASM_PFX(SErrorA32):
ASM_PFX(SynchronousExceptionEntry):
// Move the stackpointer so we can reach our structure with the str instruction.
sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
// Save all the General regs before touching x0 and x1.
// This does not save r31(SP) as it is special. We do that later.
@ -260,21 +260,21 @@ ASM_PFX(SynchronousExceptionEntry):
br x1
ASM_PFX(IrqEntry):
sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
ALL_GP_REGS
mov x0, #EXCEPT_AARCH64_IRQ
ldr x1, ASM_PFX(CommonExceptionEntry)
br x1
ASM_PFX(FiqEntry):
sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
ALL_GP_REGS
mov x0, #EXCEPT_AARCH64_FIQ
ldr x1, ASM_PFX(CommonExceptionEntry)
br x1
ASM_PFX(SErrorEntry):
sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
ALL_GP_REGS
mov x0, #EXCEPT_AARCH64_SERROR
ldr x1, ASM_PFX(CommonExceptionEntry)
@ -321,19 +321,19 @@ ASM_PFX(AsmCommonExceptionEntry):
mrs x5, far_el2 // EL1 Fault Address Register
// Adjust SP to save next set
3:add sp, sp, FP_CONTEXT_SIZE
3:add sp, sp, #FP_CONTEXT_SIZE
// Push FP regs to Stack.
ALL_FP_REGS
// Adjust SP to save next set
add sp, sp, SYS_CONTEXT_SIZE
add sp, sp, #SYS_CONTEXT_SIZE
// Save the SYS regs
ALL_SYS_REGS
// Point to top of struct after all regs saved
sub sp, sp, GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
sub sp, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
// x0 still holds the exception type.
// Set x1 to point to the top of our struct on the Stack
@ -360,7 +360,7 @@ ASM_PFX(AsmCommonExceptionEntry):
#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) ldr REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
// Adjust SP to pop system registers
add sp, sp, GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
add sp, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
ALL_SYS_REGS
EL1_OR_EL2(x6)
@ -377,17 +377,17 @@ ASM_PFX(AsmCommonExceptionEntry):
msr far_el2, x5 // EL1 Fault Address Register
3:// pop all regs and return from exception.
sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
ALL_GP_REGS
// Adjust SP to pop next set
add sp, sp, FP_CONTEXT_SIZE
add sp, sp, #FP_CONTEXT_SIZE
// Pop FP regs to Stack.
ALL_FP_REGS
// Adjust SP to be where we started from when we came into the handler.
// The handler can not change the SP.
add sp, sp, SYS_CONTEXT_SIZE
add sp, sp, #SYS_CONTEXT_SIZE
eret