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ArmPlatformPkg: Timer access for non-secure EL1/0 

According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A";
the primary CPU must be configured such that 'Timer access must be
provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and
EL1PCEN in register CNTHCTL_EL2.'

This commit adds this missing set-up to the PrePi and PrePeiCore
modules.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Sami Mujawar 2017-05-16 11:10:45 +01:00 committed by Leif Lindholm
parent 23d6348f92
commit 0e07733023
2 changed files with 16 additions and 2 deletions
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9
ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
View File

@ -1,5 +1,5 @@
#========================================================================================
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
# Copyright (c) 2011-2017, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -36,6 +36,13 @@ ASM_FUNC(SetupExceptionLevel2)
msr cptr_el2, xzr // Disable copro traps to EL2
// Enable Timer access for non-secure EL1 and EL0
// The cnthctl_el2 register bits are architecturally
// UNKNOWN on reset.
// Disable event stream as it is not in use at this stage
mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)
msr cnthctl_el2, x0
ret
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

9
ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c
View File

@ -1,6 +1,6 @@
/** @file
*
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
* Copyright (c) 2011-2017, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@ -29,5 +29,12 @@ ArchInitialize (
if (ArmReadCurrentEL () == AARCH64_EL2) {
// Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2
ArmWriteHcr (ARM_HCR_TGE);
/* Enable Timer access for non-secure EL1 and EL0
The cnthctl_el2 register bits are architecturally
UNKNOWN on reset.
Disable event stream as it is not in use at this stage
*/
ArmWriteCntHctl (CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN);
}
}