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UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm
Combine PageTables1G.asm and PageTables2M.asm to reuse code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
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@ -2,7 +2,7 @@
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; @file
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; This file includes all other code files to assemble the reset vector code
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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@ -38,11 +38,7 @@
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%include "PageTables.inc"
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%ifdef ARCH_X64
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%ifdef PAGE_TABLE_1G
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%include "X64/PageTables1G.asm"
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%else
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%include "X64/PageTables2M.asm"
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%endif
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%include "X64/PageTables.asm"
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%endif
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%ifdef DEBUG_PORT80
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@ -1,10 +1,11 @@
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;------------------------------------------------------------------------------
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; @file
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; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
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; Emits Page Tables for 1:1 mapping.
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; If using 1G page table, map addresses 0 - 0x8000000000 (512GB),
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; else, map addresses 0 - 0x100000000 (4GB)
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;
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; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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; Linear-Address Translation to a 1-GByte Page
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;
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;------------------------------------------------------------------------------
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@ -36,6 +37,7 @@ BITS 64
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PAGE_NLE_ATTR)
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%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)
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%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
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ALIGN 16
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@ -46,14 +48,36 @@ Pml4:
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DQ PAGE_NLE(Pdp)
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TIMES 0x1000 - ($ - Pml4) DB 0
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%ifdef PAGE_TABLE_1G
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Pdp:
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;
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; Page-directory pointer table (512 * 1GB entries => 512GB)
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;
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%assign i 0
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%rep 512
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DQ PAGE_PDPTE_1GB(i)
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%assign i i+1
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%endrep
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%assign i 0
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%rep 512
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DQ PAGE_PDPTE_1GB(i)
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%assign i i+1
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%endrep
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%else
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Pdp:
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;
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; Page-directory pointer table (4 * 1GB entries => 4GB)
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;
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DQ PAGE_NLE(Pd)
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DQ PAGE_NLE(Pd + 0x1000)
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DQ PAGE_NLE(Pd + 0x2000)
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DQ PAGE_NLE(Pd + 0x3000)
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TIMES 0x1000 - ($ - Pdp) DB 0
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Pd:
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;
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; Page-Directory (2048 * 2MB entries => 4GB)
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; Four pages below, each is pointed by one entry in Pdp.
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;
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%assign i 0
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%rep 0x800
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DQ PAGE_PDE_2MB(i)
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%assign i i+1
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%endrep
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%endif
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EndOfPageTables:
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@ -1,63 +0,0 @@
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;------------------------------------------------------------------------------
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; @file
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; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
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;
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; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 64
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%define ALIGN_TOP_TO_4K_FOR_PAGING
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;
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; Page table big leaf entry attribute:
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; PDPTE 1GB entry or PDE 2MB entry
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;
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%define PAGE_BLE_ATTR (PAGE_SIZE + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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;
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; Page table non-leaf entry attribute
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;
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%define PAGE_NLE_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_NLE(address) (ADDR_OF(address) + \
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PAGE_NLE_ATTR)
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%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
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Pml4:
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;
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; PML4 (1 * 512GB entry)
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;
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DQ PAGE_NLE(Pdp)
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TIMES 0x1000 - ($ - Pml4) DB 0
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Pdp:
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;
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; Page-directory pointer table (4 * 1GB entries => 4GB)
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;
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DQ PAGE_NLE(Pd)
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DQ PAGE_NLE(Pd + 0x1000)
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DQ PAGE_NLE(Pd + 0x2000)
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DQ PAGE_NLE(Pd + 0x3000)
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TIMES 0x1000 - ($ - Pdp) DB 0
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Pd:
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;
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; Page-Directory (2048 * 2MB entries => 4GB)
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; Four pages below, each is pointed by one entry in Pdp.
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;
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%assign i 0
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%rep 0x800
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DQ PAGE_PDE_2MB(i)
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%assign i i+1
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%endrep
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EndOfPageTables:
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